Sang-uhn Cha

According to our database¹, Sang-uhn Cha authored at least 5 papers between 2007 and 2020.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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2020

22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2013

Self-correcting check bit generator of error correction codes for memories.

[BibT_eX]

[DOI]

Sang-uhn Cha

Hongil Yoon

IEICE Electron. Express, 2013

2007

High Speed, Minimal Area, and Low Power SEC Code for DRAMs with Large I/O Data Widths.

[BibT_eX]

[DOI]

Sang-uhn Cha

Hongil Yoon

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Sang-uhn Cha

Timeline

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