Joao P. Bastos

According to our database, Joao P. Bastos authored at least 9 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Advanced RTN Analysis on 3D NAND Trench Devices Using Physics-Informed Machine Learning Framework.

Yusuke Higashi, Anirudh Varanasi, Philippe J. Roussel, Pablo Saraza-Canflanca, J. P. Bastos, Alexander Grill, E. Catapano, R. Asanovski, Jacopo Franco, Ben Kaczer, Adrian Chasin, Devin Verreck, S. Ramesh, Laurent Breuil, Antonio Arreghini, S. Rachidi, Y. Jeong, Geert Van den Bosch, Maarten Rosmeulen, Robin Degraeve

Proceedings of the IEEE International Reliability Physics Symposium, 2025

Dielectric Breakdown Analysis on Bottom and Top-Gated IGZO-TFT.

Simon Van Beek, Adrian Vaisman Chasin, Subhali Subhechha, Harold Dekkers, Nouredine Rassoul, Yiqun Wan, Hongwei Tang, Joao P. Bastos, Attilio Belmonte, Gouri Sankar Kar

Proceedings of the IEEE International Reliability Physics Symposium, 2025

Gate Stack Development for Next Gen High Voltage Periphery DRAM Devices.

J. P. Bastos, Jacopo Franco, Barry J. O'Sullivan, Yusuke Higashi, Adrian Chasin, J. Ganguly, Hiroaki Arimura, Alessio Spessot, M.-S. Kim, N. Horiguchi

Proceedings of the IEEE International Reliability Physics Symposium, 2025

2024

Investigation of the Impact of Ferroelectricity Boosted Gate Stacks for 3D NAND on Short Time Data Retention and Endurance.

Yusuke Higashi, J. P. Bastos, Adrian Vaisman Chasin, Laurent Breuil, Antonio Arreghini, S. Ramesh, S. Rachidi, Y. Jeong, Geert Van den Bosch, Maarten Rosmeulen

Proceedings of the IEEE International Reliability Physics Symposium, 2024

Side and Corner Region Non-Uniformities in Grown SiO2 and Their Implications on Current, Capacitance and Breakdown Characteristics.

J. P. Bastos, Barry J. O'Sullivan, Yusuke Higashi, Adrian Vaisman Chasin, Jacopo Franco, Hiroaki Arimura, J. Ganguly, Elena Capogreco, Alessio Spessot, N. Horiguchi

Proceedings of the IEEE International Reliability Physics Symposium, 2024

2022

High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories.

Romain Ritzenthaler, Elena Capogreco, E. Dupuy, Hiroaki Arimura, J. P. Bastos, P. Favia, F. Sebaai, D. Radisic, V. T. H. Nguyen, G. Mannaert, B. T. Chan, V. Machkaoutsan, Y. Yoon, H. Itokawa, M. Yamaguchi, Y. Chen, Pierre Fazan, S. Subramanian, Alessio Spessot, E. Dentoni Litta, S. Samavedam, Naoto Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery.

J. P. Bastos, Barry J. O'Sullivan, Jacopo Franco, Stanislav Tyaginov, Brecht Truijen, Adrian Vaisman Chasin, Robin Degraeve, Ben Kaczer, Romain Ritzenthaler, Elena Capogreco, E. Dentoni Litta, Alessio Spessot, Yusuke Higashi, Y. Yoon, V. Machkaoutsan, Pierre Fazan, N. Horiguchi

Proceedings of the IEEE International Reliability Physics Symposium, 2022

Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations.

Alessio Spessot, Shairfe Muhammad Salahuddin, Ricardo Escobar, Romain Ritzenthaler, Yang Xiang, Rahul Budhwani, Eugenio Dentoni Litta, Elena Capogreco, Joao P. Bastos, Yangyin Chen, Naoto Horiguchi

Proceedings of the IEEE International Memory Workshop, 2022

High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction.

Laurent Breuil, L. Nyns, S. Rachidi, K. Banerjee, Antonio Arreghini, J. P. Bastos, S. Ramesh, Geert Van den Bosch, Maarten Rosmeulen

Proceedings of the IEEE International Memory Workshop, 2022