Hiroaki Arimura
According to our database1,
Hiroaki Arimura
authored at least 8 papers
between 2013 and 2023.
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Bibliography
2023
Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper.
Proceedings of the International Conference on IC Design and Technology, 2021
2016
Proceedings of the International Conference on IC Design and Technology, 2016
2013
Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors.
Proceedings of the European Solid-State Device Research Conference, 2013