Eugenio Dentoni Litta

According to our database1, Eugenio Dentoni Litta authored at least 16 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Integration of a Stacked Contact MOL for Monolithic CFET.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations.
Proceedings of the IEEE International Memory Workshop, 2022

2021
Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper.
Proceedings of the International Conference on IC Design and Technology, 2021

2020
Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2015
Step tunneling-enhanced hot-electron injection in vertical graphene base transistors.
Proceedings of the 45th European Solid State Device Research Conference, 2015

2014
Improved low-frequency noise for 0.3nm EOT thulium silicate interfacial layer.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2013
Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs.
Proceedings of the European Solid-State Device Research Conference, 2013


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