Kang Wook Lee

Affiliations:
  • Tohoku University, Sendai, Japan


According to our database1, Kang Wook Lee authored at least 31 papers between 1998 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2016
Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration.
Micromachines, 2016

Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

New concept of TSV formation methodology using Directed Self-Assembly (DSA).
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

3D memory chip stacking by multi-layer self-assembly technology.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Development of via-last 3D integration technologies using a new temporary adhesive system.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2011
Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration.
Micromachines, 2011

Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

A very low area ADC for 3-D stacked CMOS image processing system.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Chip-level TSV integration for rapid prototyping of 3D system LSIs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Temporary bonding strength control for self-assembly-based 3D integration.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

A block-parallel signal processing system for CMOS image sensor with three-dimensional structure.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Heterogeneous integration technology for MEMS-LSI multi-chip module.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

A parallel ADC for high-speed CMOS image processing system with 3D structure.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

3D integration technology for 3D stacked retinal chip.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2000
Smart Vision Chip Fabricated Using Three Dimensional Integration Technology.
Proceedings of the Advances in Neural Information Processing Systems 13, 2000

1998
Future system-on-silicon LSI chips.
IEEE Micro, 1998


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