Mark A. Ferriss

According to our database, Mark A. Ferriss authored at least 21 papers between 2005 and 2020.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2020

A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage.

Bodhisatwa Sadhu, Alberto Valdes-Garcia, Jean-Olivier Plouchart, Herschel A. Ainspan, Arpit K. Gupta, Mark A. Ferriss, Mark Yeck, Mihai Sanduleanu, Xiaoxiong Gu, Christian W. Baks, Duixian Liu, Daniel J. Friedman

IEEE J. Solid State Circuits, 2020

2018

A 128-element Dual-Polarized Software-Defined Phased Array Radio for mm-wave 5G Experimentation.

Bodhisatwa Sadhu, Arun Paidimarri, Mark A. Ferriss, Mark Yeck, Xiaoxiong Gu, Alberto Valdes-Garcia

Proceedings of the 2nd ACM Workshop on Millimeter Wave Networks and Sensing Systems, 2018

2017

A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications.

Bodhisatwa Sadhu, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Mark A. Ferriss, Duixian Liu, Daniel J. Friedman, Alberto Valdes-Garcia

IEEE J. Solid State Circuits, 2017

2016

10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs.

Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance.

Bodhisatwa Sadhu, Mark A. Ferriss, Alberto Valdes-Garcia

IEEE J. Solid State Circuits, 2015

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman

IEEE J. Solid State Circuits, 2015

10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme.

Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits.

Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 28 GHz Hybrid PLL in 32 nm SOI CMOS.

Mark A. Ferriss, Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Daniel J. Friedman

IEEE J. Solid State Circuits, 2014

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.

Jean-Olivier Plouchart, Mark A. Ferriss, A. S. Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing.

Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman

IEEE J. Solid State Circuits, 2013

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.

Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Daniel J. Friedman

IEEE J. Solid State Circuits, 2013

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion.

Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, A. S. Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.

Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman

Proceedings of the Symposium on VLSI Circuits, 2012

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.

Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

Indirect phase noise sensing for self-healing voltage controlled oscillators.

Soner Yaldiz, Vehbi Calayir, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, José A. Tierno

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2009

A fractional-N PLL modulator with flexible direct digital phase modulation.

Mark A. Ferriss, David T. Lin, Michael P. Flynn

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme.

Mark A. Ferriss, Michael P. Flynn

IEEE J. Solid State Circuits, 2008

2007

A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching Scheme.

Mark A. Ferriss, Michael P. Flynn

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005

A 12.5-mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback.

Declan Dalton, Kwet Chai, Eric Evans, Mark A. Ferriss, Dave Hitchcox, Paul Murray, Sivanendra Selvanayagam, Paul Shepherd, Lawrence DeVito

IEEE J. Solid State Circuits, 2005