S. Biesemans
According to our database1,
S. Biesemans
authored at least 4 papers
between 2007 and 2023.
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Bibliography
2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2007
Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V V<sub>t</sub> Ni-FUSI CMOS transistors.
Microelectron. Reliab., 2007