Roger Loo

Orcid: 0000-0003-3513-6058

According to our database1, Roger Loo authored at least 7 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2023
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Comprehensive 300 mm process for Silicon spin qubits with modular integration.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

NPN Si/SiGe memory selector with non-linearity>10<sup>5</sup> and ON-current>6MA/cm<sup>2</sup>.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
60Gb/s waveguide-coupled O-band GeSi quantum-confined Stark effect electro-absorption modulator.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

2018
Scalability comparison between raised- and embedded-SiGe source/drain structures for Si<sub>0.55</sub>Ge<sub>0.45</sub> implant free quantum well pFET.
Microelectron. Reliab., 2018


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