An De Keersgieter
According to our database1,
An De Keersgieter
authored at least 11 papers
between 2002 and 2023.
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Bibliography
2023
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-Channel Transistors.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling.
Proceedings of the International Conference on IC Design and Technology, 2022
2017
Proceedings of the 47th European Solid-State Device Research Conference, 2017
2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
2013
STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process.
Proceedings of the European Solid-State Device Research Conference, 2013
2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2002
Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study.
Microelectron. Reliab., 2002