Stephen K. Sunter

According to our database¹, Stephen K. Sunter authored at least 42 papers between 1995 and 2016.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2016

Streaming Access to ADCs and DACs for Mixed-Signal ATPG.

[BibT_eX]

[DOI]

Stephen K. Sunter

Jean-Francois Cote

Jeff Rearick

IEEE Des. Test, 2016

2015

Streaming fast access to ADCs and DACs for mixed-signal ATPG.

[BibT_eX]

[DOI]

Stephen K. Sunter

Jean-Francois Cote

Jeff Rearick

Proceedings of the 2015 IEEE International Test Conference, 2015

2014

Innovative practices session 7C: Reduced pin-count testing - How low can we go?

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Innovative practices session 4C: Disruptive solutions in the non-digital world.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

2013

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Oscillation-Based Prebond TSV Test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Mid-bond Interposer Wire Test.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan.

[BibT_eX]

[DOI]

Stephen K. Sunter

Aubin Roy

IEEE Des. Test Comput., 2012

A unified method for parametric fault characterization of post-bond TSVs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Small delay testing for TSVs in 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan.

[BibT_eX]

[DOI]

Stephen K. Sunter

Aubin Roy

Proceedings of the 2011 IEEE International Test Conference, 2011

A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution.

[BibT_eX]

[DOI]

Stephen K. Sunter

Aubin Roy

Proceedings of the 16th European Test Symposium, 2011

2010

BIST of I/O circuit parameters via standard boundary scan.

[BibT_eX]

[DOI]

Stephen K. Sunter

Matthias Tilmann

Proceedings of the 2011 IEEE International Test Conference, 2010

Experiences with parametric BIST for production testing PLLs with picosecond precision.

[BibT_eX]

[DOI]

Rakesh Kinger

Swetha Narasimhawsamy

Stephen K. Sunter

Proceedings of the 2011 IEEE International Test Conference, 2010

A Configurable RDF Editor for Australian Curriculum.

[BibT_eX]

[DOI]

Proceedings of the Role of Digital Libraries in a Time of Global Change, 2010

2009

Testing bridges to nowhere - combining Boundary Scan and capacitive sensing.

[BibT_eX]

[DOI]

Steve Sunter

Kenneth P. Parker

Proceedings of the 2009 IEEE International Test Conference, 2009

2008

Noise-Insensitive Digital BIST for any PLL or DLL.

[BibT_eX]

[DOI]

Stephen K. Sunter

Aubin Roy

J. Electron. Test., 2008

2007

A selt-testing BOST for high-frequency PLLs, DLLs, and SerDes.

[BibT_eX]

[DOI]

Stephen K. Sunter

Aubin Roy

Proceedings of the 2007 IEEE International Test Conference, 2007

Purely Digital BIST for Any PLL or DLL.

[BibT_eX]

[DOI]

Stephen K. Sunter

Aubin Roy

Proceedings of the 12th European Test Symposium, 2007

Testing SerDes beyond 4 Gbps - changing priorities.

[BibT_eX]

[DOI]

Stephen K. Sunter

Aubin Roy

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Structural Tests for Jitter Tolerance in SerDes Receivers.

[BibT_eX]

[DOI]

Stephen K. Sunter

Aubin Roy

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Analog and mixed signal test techniques for SOC development.

[BibT_eX]

[DOI]

Bozena Kaminska

Stephen K. Sunter

Salvador Mir

Microelectron. J., 2005

Correct by construction is guaranteed to fail.

[BibT_eX]

[DOI]

Stephen K. Sunter

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz.

[BibT_eX]

[DOI]

Stephen K. Sunter

Aubin Roy

IEEE Des. Test Comput., 2004

An Automated, Complete, Structural Test Solution for SERDES.

[BibT_eX]

[DOI]

Stephen K. Sunter

Aubin Roy

Jean-Francois Cote

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Status of IEEE Testability Standards 1149.4, 1532 and 1149.6.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2003

Testing High Frequency ADCs and DACs with a Low Frequency Analog Bus.

[BibT_eX]

[DOI]

Stephen K. Sunter

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost.

[BibT_eX]

[DOI]

Stephen K. Sunter

Benoit Nadeau-Dostie

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

IC Mixed-Signal BIST: Separating Facts from Fiction.

[BibT_eX]

[DOI]

Stephen K. Sunter

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

High Accuracy Stimulus Generation for A/D Converter BIST.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Contactless digital testing of IC pin leakage currents.

[BibT_eX]

[DOI]

Stephen K. Sunter

Charles McDonald

Givargis Danialy

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A general purpose 1149.4 IC with HF analog test capabilities.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

How Should Fault Coverage Be Defined?

[BibT_eX]

[DOI]

Thomas W. Williams

Stephen K. Sunter

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

1999

Analog, digital, and mixed-signal people.

[BibT_eX]

Stephen K. Sunter

IEEE Des. Test Comput., 1999

Test Metrics for Analog Parametric Faults.

[BibT_eX]

[DOI]

Stephen K. Sunter

Naveena Nagi

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

BIST for phase-locked loops in digital applications.

[BibT_eX]

[DOI]

Stephen K. Sunter

Aubin Roy

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

BIST vs. ATE: need a different vehicle?

[BibT_eX]

[DOI]

Stephen K. Sunter

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST.

[BibT_eX]

[DOI]

Stephen K. Sunter

Naveena Nagi

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

P1149.4-Problem or Solution for Mixed-Signal IC Design?

[BibT_eX]

[DOI]

Stephen K. Sunter

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996

Design for testability of integrated operational amplifiers using oscillation-test strategy.

[BibT_eX]

[DOI]

Karim Arabi

Bozena Kaminska

Stephen K. Sunter

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995

A low cost 100 MHz analog test bus.

[BibT_eX]

[DOI]

Stephen K. Sunter

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

The P1149.4 Mixed Signal Test Bus: Costs and Benefits.

[BibT_eX]

[DOI]

Stephen K. Sunter

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Stephen K. Sunter

Timeline

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On csauthors.net:

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