Takeshi Hioka

According to our database, Takeshi Hioka authored at least 4 papers between 2009 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-Energy-Efficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Termination I/Os.

Kosuke Yanagidaira, Mario Sako, Yasuhiro Hirashima, Junya Matsuno, Yumi Higashi, Yutaka Shimizu, Akihiro Imamoto, Kazuaki Kawaguchi, Koji Tabata, Takeshi Nakano, Yusuke Ochi, Hiroaki Hoshino, Takeshi Hioka, Shigehito Saigusa, Hiroki Date, Masaki Unno, Jumpei Sato, You Kamata, Hardwell Chibvongodze, Naoki Ojima, Hiroshi Sugawara, Masahiro Kano, Jang-woo Lee, Hiroyuki Mizukoshi, Ryuji Yamashita, Kensaku Abe, Naohito Morozumi, In-Soo Yoon, Takuya Ariki, Jong Hak Yuh, Khin Htoo, Yosuke Kato, Yoshihisa Watanabe, Toshiyuki Kouchi

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2021

30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology.

Tsutomu Higuchi, Takuyo Kodama, Koji Kato, Ryo Fukuda, Naoya Tokiwa, Mitsuhiro Abe, Teruo Takagiwa, Yuki Shimizu, Junji Musha, Katsuaki Sakurai, Jumpei Sato, Tetsuaki Utsumi, Kazuhide Yoneya, Yasuhiro Suematsu, Toshifumi Hashimoto, Takeshi Hioka, Kosuke Yanagidaira, Masatsugu Kojima, Junya Matsuno, Kei Shiraishi, Kensuke Yamamoto, Shintaro Hayashi, Tomoharu Hashiguchi, Kazuko Inuzuka, Akio Sugahara, Mitsuaki Honma, Keiji Tsunoda, Kazumasa Yamamoto, Takahiro Sugimoto, Tomofumi Fujimura, Mizuki Kaneko, Hiroki Date, Osamu Kobayashi, Takatoshi Minamoto, Ryoichi Tachibana, Itaru Yamaguchi, Juan Lee, Venky Ramachandra, Srinivas Rajendra, Tianyu Tang, Siddhesh Darne, Jiwang Lee, Jason Li, Toru Miwa, Ryuji Yamashita, Hiroshi Sugawara, Naoki Ookuma, Masahiro Kano, Hiroyuki Mizukoshi, Yuki Kuniyoshi, Mitsuyuki Watanabe, Kei Akiyama, Hirotoshi Mori, Akira Arimizu, Yoshito Katano, Masakazu Ehama, Hiroshi Maejima, Koji Hosono, Masahiro Yoshihara

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2010

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes.

Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama

IEEE J. Solid State Circuits, 2010

2009

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes.

Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama

Proceedings of the IEEE International Solid-State Circuits Conference, 2009