Yifan He

Orcid: 0009-0001-8664-037X

Affiliations:

Reconova Technologies Company Ltd., Xiamen, China
Eindhoven University of Technology, Department of Electrical Engineering, Netherlands (PhD 2013)
NXP Semiconductors, Netherlands

According to our database¹, Yifan He authored at least 50 papers between 2008 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

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In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2025

An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., July, 2025

23.4 Nebula: A 28nm 109.8TOPS/W 3D PNN Accelerator Featuring Adaptive Partition, Multi-Skipping, and Block-Wise Aggregation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

SoftAct: A High-Precision Softmax Architecture for Transformers Supporting Nonlinear Functions.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., September, 2024

Toward Effective Traffic Sign Detection via Two-Stage Fusion Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Intell. Transp. Syst., August, 2024

A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, August, 2024

Adjustable Multi-Stream Block-Wise Farthest Point Sampling Acceleration in Point Cloud Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, May, 2024

A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A Multilevel Guidance-Exploration Network and Behavior-Scene Matching Method for Human Behavior Anomaly Detection.

[BibT_eX]

[DOI]

Proceedings of the 32nd ACM International Conference on Multimedia, MM 2024, Melbourne, VIC, Australia, 28 October 2024, 2024

A Collaborative Framework Using Multimodal Data and Adaptive Noise for Human Behavior Anomaly Detection.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2024

Selective Domain-Invariant Feature for Generalizable Deepfake Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2024

Diversity-Authenticity Co-constrained Stylization for Federated Domain Generalization in Person Re-identification.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023

CNN Accelerator at the Edge With Adaptive Zero Skipping and Sparsity-Driven Data Flow.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., December, 2023

Sagitta: An Energy-Efficient Sparse 3D-CNN Accelerator for Real-Time 3-D Understanding.

[BibT_eX]

[DOI]

IEEE Internet Things J., 2023

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro.

[BibT_eX]

[DOI]

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

An Energy-Efficient 3D Point Cloud Neural Network Accelerator With Efficient Filter Pruning, MLP Fusion, and Dual-Stream Sampling.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022

STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

PBDE: an effective post-processing method based on box density for object detection.

[BibT_eX]

[DOI]

Appl. Intell., 2022

An Efficient Framework for Detection and Recognition of Numerical Traffic Signs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2022

An LUT-Based Multiplier Array for Systolic Array-Based Convolutional Neural Network Accelerator.

[BibT_eX]

[DOI]

Ming Liu

Yifan He

Hailong Jiao

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

An Effective Face Anti-Spoofing Method via Stereo Matching.

[BibT_eX]

[DOI]

IEEE Signal Process. Lett., 2021

Correction to: A compression pipeline for one-stage object detection model.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2021

A compression pipeline for one-stage object detection model.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2021

An Energy-Efficient Low-Latency 3D-CNN Accelerator Leveraging Temporal Locality, Full Zero-Skipping, and Hierarchical Load Balance.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Efficient Zero-Activation-Skipping for On-Chip Low-Energy CNN Acceleration.

[BibT_eX]

[DOI]

Min Liu

Yifan He

Hailong Jiao

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2019

Automatic Memory-Efficient Scheduling of CNNs.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

2018

Crosstalk-noise-aware bus coding with low-power ground-gated repeaters.

[BibT_eX]

[DOI]

Hailong Jiao

Rui Wang

Yifan He

Int. J. Circuit Theory Appl., 2018

Datawidth-Aware Energy-Efficient Multipliers: A Case for Going Sign Magnitude.

[BibT_eX]

[DOI]

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2016

A configurable SIMD architecture with explicit datapath for intelligent learning.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

MacSim: A MAC-Enabled High-Performance Low-Power SIMD Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015

A Low-Energy Wide SIMD Architecture with Explicit Datapath.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2015

A Co-Design Framework with OpenCL Support for Low-Energy Wide SIMD Processor.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2015

2014

Reduction Operator for Wide-SIMDs Reconsidered.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

An energy-efficient method of supporting flexible special instructions in an embedded processor with compact ISA.

[BibT_eX]

[DOI]

Dongrui She

Yifan He

Henk Corporaal

ACM Trans. Archit. Code Optim., 2013

Efficient communication support in predictable heterogeneous MPSoC designs for streaming applications.

[BibT_eX]

[DOI]

J. Syst. Archit., 2013

SIMD made explicit.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

OpenCL code generation for low energy wide SIMD architectures with explicit datapath.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

MAMPSx: A design framework for rapid synthesis of predictable heterogeneous MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

Scheduling for register file energy minimization in explicit datapath architectures.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Energy efficient special instruction support in an embedded processor with compact isa.

[BibT_eX]

[DOI]

Dongrui She

Yifan He

Henk Corporaal

Proceedings of the 15th International Conference on Compilers, 2012

2011

From Xetal-II to Xetal-Pro: On the Road Toward an Ultralow-Energy and High-Throughput SIMD Processor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2011

MOVE-Pro: A low power and high code density TTA architecture.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Bottlenecks and Tradeoffs in High Frame Rate Visual Servoing: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the IAPR Conference on Machine Vision Applications (IAPR MVA 2011), 2011

Demo: An embedded vision system for high frame rate visual servoing.

[BibT_eX]

[DOI]

Proceedings of the 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, 2011

Feasibility Analysis of Ultra High Frame Rate Visual Servoing on FPGA and SIMD Processor.

[BibT_eX]

[DOI]

Proceedings of the Advances Concepts for Intelligent Vision Systems, 2011

2010

Xetal-Pro: an ultra-low energy and high throughput SIMD processor.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2008

Real-time implementations of Hough Transform on SIMD architecture.

[BibT_eX]

[DOI]

Proceedings of the 2008 Second ACM/IEEE International Conference on Distributed Smart Cameras, 2008

Real-Time Hough Transform on 1-D SIMD Processors: Implementation and Architecture Exploration.

[BibT_eX]

[DOI]

Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2008

Yifan He

Timeline

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