Danielle Duvalsaint

According to our database, Danielle Duvalsaint authored at least 7 papers between 2019 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

PEPR: Pseudo-Exhaustive Physically-Aware Region Testing.

Wei Li, Chris Nigh, Danielle Duvalsaint, Subhasish Mitra, Ronald D. Blanton

Proceedings of the IEEE International Test Conference, 2022

Secuirty Metrics for Logic Circuits.

Ruben Purdy, Danielle Duvalsaint, R. D. Shawn Blanton

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021

Characterizing Corruptibility of Logic Locks using ATPG.

Danielle Duvalsaint, R. D. Shawn Blanton

Proceedings of the IEEE International Test Conference, 2021

2020

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.

Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks

CoRR, 2020

Special Session: Novel Attacks on Logic-Locking.

Ayush Jain, Ujjwal Guin, M. Tanjidur Rahman, Navid Asadizanjani, Danielle Duvalsaint, R. D. Shawn Blanton

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

2019

Characterization of Locked Combinational Circuits via ATPG.

Danielle Duvalsaint, Xiaoxiao Jin, Benjamin Niewenhuis, R. D. (Shawn) Blanton

Proceedings of the IEEE International Test Conference, 2019

Characterization of Locked Sequential Circuits via ATPG.

Danielle Duvalsaint, Zeye Liu, Ananya Ravikumar, Ronald D. Blanton

Proceedings of the IEEE International Test Conference in Asia, 2019