Peter Gadfort

Orcid: 0000-0002-2591-7670

According to our database1, Peter Gadfort authored at least 7 papers between 2014 and 2021.

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Bibliography

2021
FPNA: A Reconfigurable Accelerator for AI Inference at the Edge.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

2020
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.
CoRR, 2020

2018
RF-Only Logic: an Area Efficient Logic Family for RF-Power Harvesting Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Hardware Implementation of an Adaptive Data Acquisition System for Real-World EEG.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

2017
Online adaptive data acquisition enabling ultra-low power real-world EEG.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2014
A power efficient reconfigurable system-in-stack: 3D integration of accelerators, FPGAs, and DRAM.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Split-fabrication obfuscation: Metrics and techniques.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014


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