Abhrajit Sengupta

Orcid: 0000-0002-5491-6714

According to our database1, Abhrajit Sengupta authored at least 23 papers between 2014 and 2023.

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Bibliography

2023
A Needle in the Haystack: Inspecting Circuit Layout to Identify Hardware Trojans.
IACR Cryptol. ePrint Arch., 2023

UN-SPLIT: Attacking Split Manufacturing Using Link Prediction in Graph Neural Networks.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2023

2022
GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL.
Cryptogr., 2022

2021
Breaking CAS-Lock and Its Variants by Exploiting Structural Traces.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

2020
Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Logic Locking With Provable Security Against Power Analysis Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.
CoRR, 2020

2019
CAS-Unlock: Unlocking CAS-Lock without Access to a Reverse-Engineered Netlist.
IACR Cryptol. ePrint Arch., 2019

Logic Locking of Boolean Circuits: Provable Hardware-Based Obfuscation from a Tamper-Proof Memory.
Proceedings of the Innovative Security Solutions for Information Technology and Communications, 2019

Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access.
Proceedings of the International Conference on Computer-Aided Design, 2019

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Attacking Split Manufacturing from a Deep Learning Perspective.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
ATPG-based cost-effective, secure logic locking.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Customized locking of IP blocks on a multi-million-gate SoC.
Proceedings of the International Conference on Computer-Aided Design, 2018

Towards provably-secure performance locking.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Preventing fault attacks using fault randomisation with a case study on AES.
Int. J. Appl. Cryptogr., 2017

Rethinking split manufacturing: An information-theoretic approach with secure layout techniques.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

What to Lock?: Functional and Parametric Locking.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Provably-Secure Logic Locking: From Theory To Practice.
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security, 2017

2015
Preventing Fault Attacks Using Fault Randomization with a Case Study on AES.
Proceedings of the Information Security and Privacy - 20th Australasian Conference, 2015

2014
AEC: A Practical Scheme for Authentication with Error Correction.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2014

A Scalable Method for Constructing Non-linear Cellular Automata with Period 2 n - 1.
Proceedings of the Cellular Automata, 2014


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