Georgi Kuzmanov

According to our database1, Georgi Kuzmanov authored at least 56 papers between 2002 and 2016.

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Bibliography

2016
RTOS acceleration in an MPSoC with reconfigurable hardware.
Comput. Electr. Eng., 2016

2014
Hardware Task-Status Manager for an RTOS with FIFO communication.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

2013
Custom architecture for multicore audio beamforming systems.
ACM Trans. Embed. Comput. Syst., 2013

Run-Time Slack Distribution for Real-Time Data-Flow Applications on Embedded MPSoC.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Multithreading on reconfigurable hardware: An architectural approach.
Microprocess. Microsystems, 2012

On implementability of Polymorphic Register Files.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Scalability Study of Polymorphic Register Files.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Multi-Core Platforms for Beamforming and Wave Field Synthesis.
IEEE Trans. Multim., 2011

Vector processor customization for FFT.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Real-time high-definition stereo matching on FPGA.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Inverse Integer Transform in H.264/AVC Intra-frame Encoder.
Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

Scalability Evaluation of a Polymorphic Register File: A CG Case Study.
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011

Architectural Support for Multithreading on Reconfigurable Hardware.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

A Reconfigurable Audio Beamforming Multi-Core Processor.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms.
IEEE Micro, 2010

An efficient realization of forward integer transform in H.264/AVC intra-frame encoder.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

A Polymorphic Register File for matrix operations.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

A Minimalistic Architecture for Reconfigurable WFS-Based Immersive-Audio.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Low-power, high-throughput deblocking filter for H.264/AVC.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

SAMS multi-layout memory: providing multiple views of data to boost SIMD performance.
Proceedings of the 24th International Conference on Supercomputing, 2010

Minimalistic architecture for reconfigurable audio Beamforming.
Proceedings of the International Conference on Field-Programmable Technology, 2010

A 3d-audio reconfigurable processor.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Configurable, low-power design for inverse integer transform in H.264/AVC.
Proceedings of the FIT '10, 2010

2009
A reconfigurable beamformer for audio applications.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

Reconfigurable Multithreading Architectures: A Survey.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Reconfigurable accelerator for WFS-based 3D-audio.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

A high-throughput, area-efficient hardware accelerator for adaptive deblocking filter in H.264/AVC.
Proceedings of the 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2009

Polymorphic architectures: from media processing to supercomputing.
Proceedings of the 2009 International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, 2009

Wave field synthesis for 3D audio: architectural prospectives.
Proceedings of the 6th Conference on Computing Frontiers, 2009

2008
Cost-Efficient SHA Hardware Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., 2008

OpenFPGA CoreLib core library interoperability effort.
Parallel Comput., 2008

BRAM-LUT Tradeoff on a Polymorphic DES Design.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

On-the-fly attestation of reconfigurable hardware.
Proceedings of the FPL 2008, 2008

Memory Organization with Multi-Pattern Parallel Accesses.
Proceedings of the Design, Automation and Test in Europe, 2008

Merged Computation for Whirlpool Hashing.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Floating-Point Matrix Multiplication in a Polymorphic Processor.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator.
Proceedings of the FPL 2007, 2007

HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation.
Proceedings of the FPL 2007, 2007

2006
Multimedia rectangularly addressable memory.
IEEE Trans. Multim., 2006

Rescheduling for Optimized SHA-1 Calculation.
Proceedings of the Embedded Computer Systems: Architectures, 2006

External Memory Controller for Virtex II Pro.
Proceedings of the International Symposium on System-on-Chip, 2006

Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Reconfigurable memory based AES co-processor.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Improving SHA-2 Hardware Implementations.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

PISC: Polymorphic Instruction Set Computers.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Hardwired MPEG-4 repetitive padding.
IEEE Trans. Multim., 2005

64-bit floating-point FPGA matrix multiplication.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004
The Molen Polymorphic Media Processor.
PhD thesis, 2004

The MOLEN Polymorphic Processor.
IEEE Trans. Computers, 2004

The Virtex II Pro<sup>TM</sup> MOLEN Processor.
Proceedings of the Computer Systems: Architectures, 2004

Loading rho-µ-Code: Design Considerations.
Proceedings of the Computer Systems: Architectures, 2004

The MOLEN Processor Prototype.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Visual Data Rectangular Memory.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

2003
Arbitrating Instructions in an pmu-Coded CCM.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
A 2D Addressing Mode for Multimedia Applications.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Reconfigurable repetitive padding unit.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002


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