Kiyoo Itoh

According to our database, Kiyoo Itoh authored at least 51 papers between 1989 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays.

Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh

IEICE Trans. Electron., 2012

0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs.

Akira Kotabe, Kiyoo Itoh, Riichiro Takemura

IEICE Trans. Electron., 2012

A Low-<i>V</i>_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing.

Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh

IEICE Trans. Electron., 2012

2011

Nanoscale Memory Repair

Masashi Horiguchi, Kiyoo Itoh

Integrated Circuits and Systems, Springer, ISBN: 978-1-4419-7958-2, 2011

Embedded Memories: Progress and a Look into the Future.

Kiyoo Itoh

IEEE Des. Test Comput., 2011

Beyond the horizon: The next 10x reduction in power - Challenges and solutions.

Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs.

Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

Adaptive Circuits for the 0.5-V Nanoscale CMOS Era.

Kiyoo Itoh, Masanao Yamaoka, Takashi Oshima

IEICE Trans. Electron., 2010

Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs.

Kiyoo Itoh

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

2009

Adaptive circuits for the 0.5-V nanoscale CMOS era.

Kiyoo Itoh

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays.

Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.

Kiyoo Itoh

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008

Memory at VLSI Circuits Symposium.

Kiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi

IEEE J. Solid State Circuits, 2008

2007

Ultra-Low Voltage Nano-Scale Memories

Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka

Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-68853-4, 2007

Long-Retention-Time, High-Speed DRAM Array with 12-<i>F</i>² Twin Cell for Sub 1-V Operation.

Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara

IEICE Trans. Electron., 2007

Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs.

Kiyoo Itoh, Riichiro Takemura

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs.

Kiyoo Itoh

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.

Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Low-voltage limitations of memory-rich nano-scale CMOS LSIs.

Kiyoo Itoh, Masashi Horiguchi, Masanao Yamaoka

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006

A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-V_<i>T</i> sense amplifiers.

Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Ultra-low voltage nano-scale embedded RAMs.

Kiyoo Itoh, Masashi Horiguchi, Takayuki Kawahara

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2004

Low-Voltage Embedded RAMs - Current Status and Future Trends.

Kiyoo Itoh, Kenichi Osada, Takayuki Kawahara

Proceedings of the Integrated Circuit and System Design, 2004

Reviews and future prospects of low-voltage embedded RAMs.

Kiyoo Itoh, Kenichi Osada, Takayda Kawahara

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Review and future prospects of low-voltage RAM circuits.

Yoshinobu Nakagome, Masashi Horiguchi, Takayuki Kawahara, Kiyoo Itoh

IBM J. Res. Dev., 2003

2002

A low-impedance open-bitline array for multigigabit DRAM.

Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura

IEEE J. Solid State Circuits, 2002

Trends in Ultralow-Voltage RAM Technology.

Kiyoo Itoh

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Low-voltage memories for power-aware systems.

Kiyoo Itoh

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

2001

A multigigabit DRAM technology with 6F² open-bitline cell, distributed overdriven sensing, and stacked-flash fuse.

Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh

IEEE J. Solid State Circuits, 2001

Low-Voltage Embedded-RAM Technology: Present and Future.

Kiyoo Itoh, Hiroyuki Mizuno

Proceedings of the SOC Design Methodologies, 2001

1997

Limitations and challenges of multigigabit DRAM chip design.

Kiyoo Itoh, Yoshinobu Nakagome, Shin'ichiro Kimura, Takao Watanabe

IEEE J. Solid State Circuits, 1997

1995

Trends in low-power RAM circuit technologies.

Kiyoo Itoh, Katsuro Sasaki, Yoshinobu Nakagome

Proc. IEEE, 1995

1994

Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's.

Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki

IEEE J. Solid State Circuits, August, 1994

Subthreshold-current reduction circuits for multi-gigabit DRAM's.

Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki

IEEE J. Solid State Circuits, July, 1994

1993

Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's.

Masashi Horiguchi, Takeshi Sakata, Kiyoo Itoh

IEEE J. Solid State Circuits, November, 1993

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays.

Takayuki Kawahara, Takeshi Sakata, Kiyoo Itoh, Yoshiki Kawajiri, Takesada Akiba, Goro Kitsukawa, Masakazu Aoki

IEEE J. Solid State Circuits, July, 1993

Sub-1-V swing internal bus architecture for future low-power ULSIs.

Yoshinobu Nakagome, Kiyoo Itoh, Masanori Isoda, Kan Takeuchi, Masakazu Aoki

IEEE J. Solid State Circuits, April, 1993

A single 1.5-V digital chip for a 10⁶ synapse neural network.

Takao Watanabe, Katsutaka Kimura, Masakazu Aoki, Takeshi Sakata, Kiyoo Ito

IEEE Trans. Neural Networks, 1993

1992

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's.

Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh

IEEE J. Solid State Circuits, April, 1992

1991

A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture.

Katsutaka Kimura, Takeshi Sakata, Kiyoo Itoh, Toru Kaga, Takashi Nishida, Yoshifumi Kawamoto

IEEE J. Solid State Circuits, November, 1991

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's.

Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Yoshinobu Nakagome, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh

IEEE J. Solid State Circuits, November, 1991

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM.

Yoshinobu Nakagome, Kiyoo Itoh, Kan Takeuchi, Eiji Kume, Hitoshi Tanaka, Masanori Isoda, Tatsunori Musha, Toru Kaga, Teruaki Kisu, Takashi Nishida, Yoshifumi Kawamoto, Masakazu Aoki

IEEE J. Solid State Circuits, July, 1991

An experimental 1.5-V 64-Mb DRAM.

Yoshinobu Nakagome, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Yoshifumi Kawamoto, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, Kiyoo Itoh

IEEE J. Solid State Circuits, April, 1991

A flexible redundancy technique for high-density DRAMs.

Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Kiyoo Itoh, Tetsuro Matsumoto

IEEE J. Solid State Circuits, January, 1991

1990

A 23-ns 1-Mb BiCMOS DRAM.

Goro Kitsukawa, Kazumasa Yanagisawa, Yutaka Kobayashi, Yoshitaka Kinoshita, Tatsuyuki Ohta, Tetsu Udagawa, Hitoshi Miwa, Hiroyuki Miyazawa, Yoshiki Kawajiri, Yoshiaki Ouchi, Hiromi Tsukada, Tetsuro Matsumoto, Kiyoo Itoh

IEEE J. Solid State Circuits, October, 1990

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier.

Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga, Kiyoo Itoh, Kazuhiko Kajigaya, Hiroaki Kotani, Kazuyoshi Ohshima, Tetsuro Matsumoto

IEEE J. Solid State Circuits, October, 1990

Trends in megabit DRAM circuit design.

Kiyoo Itoh

IEEE J. Solid State Circuits, June, 1990

1989

Substrate current reduction techniques for BiCMOS DRAM.

Takayuki Kawahara, Goro Kitsukawa, Hisayuki Higuchi, Yoshiki Kawajiri, Takao Watanabe, Kiyoo Itoh, Ryoichi Hori, Yutaka Kobayashi, Tetsuro Matsumoto

IEEE J. Solid State Circuits, October, 1989

A 1.5-V DRAM for battery-based applications.

Masakazu Aoki, Jun Etoh, Kiyoo Itoh, Shin Kimura, Yoshifumi Kawamoto

IEEE J. Solid State Circuits, October, 1989

New DRAM noise generation under half-V_cc precharge and its reduction using a transposed amplifier.

Masakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh

IEEE J. Solid State Circuits, August, 1989

Comparison of CMOS and BiCMOS 1-Mbit DRAM performance.

Takao Watanabe, Goro Kitsukawa, Yoshiki Kawajiri, Kiyoo Itoh, Ryoichi Hori, Yoshiaki Ouchi, Takayuki Kawahara, Tetsuro Matsumoto

IEEE J. Solid State Circuits, June, 1989

A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques.

Goro Kitsukawa, Kiyoo Itoh, Ryoichi Hori, Yoshiki Kawajiri, Takao Watanabe, Takayuki Kawahara, Tetsuro Matsumoto, Yutaka Kobayashi

IEEE J. Solid State Circuits, June, 1989