Samira Manabi Khan

Affiliations:
  • University of Virginia, VA, USA


According to our database1, Samira Manabi Khan authored at least 56 papers between 2007 and 2024.

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Bibliography

2024
CC-NIC: a Cache-Coherent Interface to the NIC.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Side-Channel Attacks on Optane Persistent Memory.
Proceedings of the 32nd USENIX Security Symposium, 2023

A Cloud-Scale Characterization of Remote Procedure Calls.
Proceedings of the 29th Symposium on Operating Systems Principles, 2023

Profiling Hyperscale Big Data Processing.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

NearPM: A Near-Data Processing System for Storage-Class Applications.
Proceedings of the Eighteenth European Conference on Computer Systems, 2023

vPIM: Efficient Virtual Address Translation for Scalable Processing-in-Memory Architectures.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Partitioned Persist Ordering.
CoRR, 2022

Efficient 2D Graph SLAM for Sparse Sensing.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022

PIMProf: An Automated Program Profiler for Processing-in-Memory Offloading Decisions.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

PiMulator: a Fast and Flexible Processing-in-Memory Emulation Platform.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Pavise: Integrating Fault Tolerance Support for Persistent Memory Applications.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021
MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator.
IEEE Comput. Archit. Lett., 2021

Power and Thermal Modeling of In-3D-Memory Computing.
Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021

PMNet: In-Network Data Persistence.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

PMFuzz: test case generation for persistent memory programs.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

Write Prediction for Persistent Memory Systems.
Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021

2020
Cross-Failure Bug Detection in Persistent Memory Programs.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Janus: optimizing memory and storage support for non-volatile memory systems.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

PMTest: A Fast and Flexible Testing Framework for Persistent Memory Programs.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure.
CoRR, 2018

Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips.
CoRR, 2018

Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins.
CoRR, 2018

Decoupling GPU Programming Models from Resource Management for Enhanced Programming Ease, Portability, and Performance.
CoRR, 2018

Zorua: Enhancing Programming Ease, Portability, and Performance in GPUs by Decoupling Programming Models from Resource Management.
CoRR, 2018

Crash Consistency in Encrypted Non-volatile Main Memory Systems.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms.
Proc. ACM Meas. Anal. Comput. Syst., 2017

A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM.
IEEE Comput. Archit. Lett., 2017

Detecting and mitigating data-dependent DRAM failures by exploiting current memory content.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Automata-to-Routing: An Open-Source Toolchain for Design-Space Exploration of Spatial Automata Processing Architectures.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Programming for Non-Volatile Main Memory Is Hard.
Proceedings of the 8th Asia-Pacific Workshop on Systems, Mumbai, India, September 2, 2017, 2017

2016
Simultaneous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost.
ACM Trans. Archit. Code Optim., 2016

Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips.
CoRR, 2016

Adaptive-Latency DRAM (AL-DRAM).
CoRR, 2016

Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization.
Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Science, 2016

Zorua: A holistic approach to resource virtualization in GPUs.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM.
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2016

2015
Simultaneous Multi Layer Access: A High Bandwidth and Low Cost 3D-Stacked Memory Interface.
CoRR, 2015

The application slowdown model: quantifying and controlling the impact of inter-application interference at shared caches and main memory.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

ThyNVM: enabling software-transparent crash consistency in persistent memory systems.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems.
Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015

2014
The efficacy of error mitigation techniques for DRAM retention failures: a comparative experimental study.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

Last-level cache deduplication.
Proceedings of the 2014 International Conference on Supercomputing, 2014

Improving cache performance using read-write partitioning.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
Temporal-based multilevel correlating inclusive cache replacement.
ACM Trans. Archit. Code Optim., 2013

Improving multi-core performance using mixed-cell cache architecture.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012
Rank idle time prediction driven last-level cache writeback.
Proceedings of the 2012 ACM SIGPLAN workshop on Memory Systems Performance and Correctness: held in conjunction with PLDI '12, 2012

Improving writeback efficiency with decoupled last-write prediction.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Decoupled dynamic cache segmentation.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011
Decoupled Cache Segmentation: Mutable Policy with Automated Bypass.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Sampling Dead Block Prediction for Last-Level Caches.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Insertion policy selection using Decision Tree Analysis.
Proceedings of the 28th International Conference on Computer Design, 2010

Using dead blocks as a virtual victim cache.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2007
Quantum Realization of Some Ternary Circuits Using Muthukrishnan-Stroud Gates.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007


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