Xingsheng Wang
Orcid: 0000-0001-8335-2033Affiliations:
- Huazhong University of Science and Technology, School of Optical and Electronic Information, Wuhan, China
According to our database1,
Xingsheng Wang
authored at least 24 papers
between 2010 and 2025.
Collaborative distances:
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Bibliography
2025
ISARA: An Island-Style Systolic Array Reconfigurable Accelerator Based on Memristors for Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., April, 2025
Optimizing hardware-software co-design based on non-ideality in memristor crossbars for in-memory computing.
Sci. China Inf. Sci., 2025
ReBA: A Hybrid Sparse Reconfigurable Butterfly Accelerator for Solving Partial Differential Equations via Hardware and Algorithm Co-Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
A Novel Memristor-Based Majority Logic and Efficient Approximate Full Adder for Image Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Multi-Level RTN with Certain Regularities in Oxide-RRAM: Experiments, Defect Dynamics and 3D Multi-Physics Modeling.
Proceedings of the IEEE International Reliability Physics Symposium, 2025
2024
CoRR, 2024
Efficient implementation of majority-inverter graph logic and arithmetic functions with memristor arrays.
Sci. China Inf. Sci., 2024
Proceedings of the IEEE International Conference on Integrated Circuits, 2024
Multi-order Differential Neural Network for TCAD Simulation of the Semiconductor Devices.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
Modeling and physical mechanism analysis of the effect of a polycrystalline-ferroelectric gate on FE-FinFETs.
Sci. China Inf. Sci., May, 2023
A comprehensive study of device variability of sub-5 nm nanosheet transistors and interplay with quantum confinement variation.
Sci. China Inf. Sci., February, 2023
Invited Paper: A Memristor-Based Stateful Majority-Inverter Graph Logic and 1-Bit Full Adder for In-Memory Computing Systems.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
2020
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
Electrostatic Characteristics Analysis of Ferroelectric Tunneling Junctions with Different Structures.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
2019
A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond.
CoRR, 2019
2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
2014
Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability.
Proceedings of the 44th European Solid State Device Research Conference, 2014
2013
Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology.
IEEE Des. Test, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability.
Proceedings of the European Solid-State Device Research Conference, 2013
2012
Statistical variability in 14-nm node SOI FinFETs and its impact on corresponding 6T-SRAM cell design.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
2010
IEEE Des. Test Comput., 2010
Proceedings of the Design, Automation and Test in Europe, 2010