Yuhao Wang

Orcid: 0000-0002-9724-9667

Affiliations:
  • Nanyang Technological University, School of Electrical and Electronic Engineering, Singapore (PhD 2015)


According to our database1, Yuhao Wang authored at least 25 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
HBP: Hierarchically Balanced Pruning and Accelerator Co-Design for Efficient DNN Inference.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
184QPS/W 64Mb/mm<sup>2</sup>3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021
STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Area Efficient Pattern Representation of Binary Neural Networks on RRAM.
J. Comput. Sci. Technol., 2021

2020
Learning in the Frequency Domain.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks.
Proceedings of the Advanced Computer Architecture - 13th Conference, 2020

DARB: A Density-Adaptive Regular-Block Pruning for Deep Neural Networks.
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020

2019
DARB: A Density-Aware Regular-Block Pruning for Deep Neural Networks.
CoRR, 2019

2017
Data-Driven Sampling Matrix Boolean Optimization for Energy-Efficient Biomedical Signal Acquisition by Compressive Sensing.
IEEE Trans. Biomed. Circuits Syst., 2017

2016
Non-Volatile In-Memory Computing by Spintronics
Synthesis Lectures on Emerging Engineering Technologies, Morgan & Claypool Publishers, ISBN: 978-3-031-02032-2, 2016

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory.
IEEE Trans. Inf. Forensics Secur., 2016

An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

A 3D multi-layer CMOS-RRAM accelerator for neural network.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Optimizing Boolean embedding matrix for compressive sensing in RRAM crossbar.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

A body-biasing of readout circuit for STT-RAM with improved thermal reliability.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy efficient in-memory machine learning for data intensive image-processing by non-volatile domain-wall memory.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Design Exploration of Emerging Nano-scale Non-volatile Memory.
Springer, ISBN: 978-1-4939-0550-8, 2014

2013
An ultralow-power memory-based big-data computing platform by nonvolatile domain-wall nanowire devices.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012
Design exploration of ultra-low power non-volatile memory based on topological insulator.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

2011
Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbar.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011


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