Francesco Svelto
  According to our database1,
  Francesco Svelto
  authored at least 90 papers
  between 1993 and 2022.
  
  
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
  IEEE Fellow 2013, "For contributions to analysis and design of radio frequency circuits and systems".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
  2022
    IEEE Trans. Circuits Syst. II Express Briefs, 2022
    
  
Analog Front End of 50-Gb/s SiGe BiCMOS Opto-Electrical Receiver in 3-D-Integrated Silicon Photonics Technology.
    
  
    IEEE J. Solid State Circuits, 2022
    
  
  2019
High-Efficiency SiGe-BiCMOS $E$ -Band Power Amplifiers Exploiting Current Clamping in the Common-Base Stage.
    
  
    IEEE J. Solid State Circuits, 2019
    
  
70-90-GHz Self-Tuned Polyphase Filter for Wideband I/Q LO Generation in a 55-nm BiCMOS Transmitter.
    
  
    Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
    
  
A 26-Gb/s 3-D-Integrated Silicon Photonic Receiver in BiCMOS-55 nm and PIC25G With - 15.2-dBm OMA Sensitivity.
    
  
    Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
    
  
  2018
A PVT-Tolerant >40-dB IRR, 44% Fractional-Bandwidth Ultra-Wideband mm-Wave Quadrature LO Generator for 5G Networks in 55-nm CMOS.
    
  
    IEEE J. Solid State Circuits, 2018
    
  
A K-band low-noise bipolar class-C VCO for 5G backhaul systems in 55 nm BiCMOS technology.
    
  
    Integr., 2018
    
  
A >40dB IRR, 44% fractional-bandwidth ultra-wideband mm-wave quadrature LO generator for 5G networks in 55nm CMOS.
    
  
    Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
    
  
Low phase noise K-band VCO and high efficiency E-band power amplifier for mobile network backhaul in SiGe BiCMOS.
    
  
    Proceedings of the 2018 International Conference on IC Design & Technology, 2018
    
  
  2017
Insights Into Phase-Noise Scaling in Switch-Coupled Multi-Core LC VCOs for E-Band Adaptive Modulation Links.
    
  
    IEEE J. Solid State Circuits, 2017
    
  
Design of low-power wideband frequency quadruplers based on transformer-coupled resonators for E-Band backhaul applications.
    
  
    Integr., 2017
    
  
2.6 A SiGe BiCMOS E-band power amplifier with 22% PAE at 18dBm OP1dB and 8.5% at 6dB back-off leveraging current clamping in a common-base stage.
    
  
    Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
    
  
  2016
Insights Into Silicon Photonics Mach-Zehnder-Based Optical Transmitter Architectures.
    
  
    IEEE J. Solid State Circuits, 2016
    
  
23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies.
    
  
    Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
    
  
A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links.
    
  
    Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
    
  
A multi-core VCO and a frequency quadrupler for E-Band adaptive-modulation links in 55nm BiCMOS.
    
  
    Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
    
  
  2015
A 40-67 GHz Power Amplifier With 13 dBm ℙ<sub>SAT</sub> and 16% PAE in 28 nm CMOS LP.
    
  
    IEEE J. Solid State Circuits, 2015
    
  
22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s.
    
  
    Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
    
  
    Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
    
  
  2014
Analysis and Design of a High Voltage Integrated Class-B Amplifier for Ultra-Sound Transducers.
    
  
    IEEE Trans. Circuits Syst. I Regul. Pap., 2014
    
  
    IEEE J. Solid State Circuits, 2014
    
  
    Proceedings of the ESSCIRC 2014, 2014
    
  
A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies.
    
  
    Proceedings of the ESSCIRC 2014, 2014
    
  
  2013
Analysis and Design of mm-Wave Frequency Dividers Based on Dynamic Latches With Load Modulation.
    
  
    IEEE J. Solid State Circuits, 2013
    
  
A 33.6-to-46.2GHz 32nm CMOS VCO with 177.5dBc/Hz minimum noise FOM using inductor splitting for tuning extension.
    
  
    Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
    
  
    Proceedings of 2013 International Conference on IC Design & Technology, 2013
    
  
  2012
A 90Vpp 720MHz GBW linear power amplifier for ultrasound imaging transmitters in BCD6-SOI.
    
  
    Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
    
  
    Proceedings of the 38th European Solid-State Circuit conference, 2012
    
  
A 4.8mW inductorless CMOS frequency divider-by-4 with more than 60% fractional bandwidth up to 70GHz.
    
  
    Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
    
  
  2011
    IEEE Trans. Circuits Syst. I Regul. Pap., 2011
    
  
    IEEE J. Solid State Circuits, 2011
    
  
A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves.
    
  
    IEEE J. Solid State Circuits, 2011
    
  
    Proceedings of the IEEE International Solid-State Circuits Conference, 2011
    
  
    Proceedings of the IEEE International Solid-State Circuits Conference, 2011
    
  
  2010
Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs.
    
  
    IEEE Trans. Circuits Syst. I Regul. Pap., 2010
    
  
A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation.
    
  
    IEEE J. Solid State Circuits, 2010
    
  
    IEEE J. Solid State Circuits, 2010
    
  
A Low Phase-Noise Multi-Phase LO Generator for Wideband Demodulators Based on Reconfigurable Sub-Harmonic Mixers.
    
  
    IEEE J. Solid State Circuits, 2010
    
  
A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation.
    
  
    Proceedings of the IEEE International Solid-State Circuits Conference, 2010
    
  
A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators.
    
  
    Proceedings of the IEEE International Solid-State Circuits Conference, 2010
    
  
    Proceedings of the IEEE International Solid-State Circuits Conference, 2010
    
  
A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOS.
    
  
    Proceedings of the IEEE International Solid-State Circuits Conference, 2010
    
  
  2009
Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations.
    
  
    IEEE J. Solid State Circuits, 2009
    
  
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques.
    
  
    IEEE J. Solid State Circuits, 2009
    
  
A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication.
    
  
    IEEE J. Solid State Circuits, 2009
    
  
A reconfigurable demodulator with 3-to-5GHz agile synthesizer for 9-band WiMedia UWB in 65nm CMOS.
    
  
    Proceedings of the IEEE International Solid-State Circuits Conference, 2009
    
  
    Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
    
  
A 5.2mW ku-band CMOS injection-locked frequency doubler with differential input / output.
    
  
    Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
    
  
    Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
    
  
  2008
    IEEE J. Solid State Circuits, 2008
    
  
A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction.
    
  
    Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
    
  
A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS.
    
  
    Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
    
  
    Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
    
  
A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR.
    
  
    Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
    
  
  2007
CMOS balanced regenerative frequency dividers for wide-band quadrature LO generation.
    
  
    Microelectron. J., 2007
    
  
    IEEE J. Solid State Circuits, 2007
    
  
A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS.
    
  
    IEEE J. Solid State Circuits, 2007
    
  
    Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
    
  
    Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
    
  
  2006
A 1.8-GHz injection-locked quadrature CMOS VCO with low phase noise and high phase accuracy.
    
  
    IEEE Trans. Circuits Syst. I Regul. Pap., 2006
    
  
    Microelectron. J., 2006
    
  
    IEEE J. Solid State Circuits, 2006
    
  
    IEEE J. Solid State Circuits, 2006
    
  
    IEEE J. Solid State Circuits, 2006
    
  
    Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
    
  
A 750mV 15kHz 1/f Noise Corner 51dBm IIP2 Direct-Conversion Front-End for GSM in 90nm CMOS.
    
  
    Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
    
  
  2005
Statistical analysis of second-order intermodulation distortion in WCDMA direct conversion receivers.
    
  
    IEEE Trans. Circuits Syst. II Express Briefs, 2005
    
  
A variable gain RF front-end, based on a Voltage-Voltage feedback LNA, for multistandard applications.
    
  
    IEEE J. Solid State Circuits, 2005
    
  
    Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
    
  
    Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
    
  
    Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
    
  
  2004
    IEEE J. Solid State Circuits, 2004
    
  
A fully integrated 0.18-μm CMOS direct conversion receiver front-end with on-chip LO for UMTS.
    
  
    IEEE J. Solid State Circuits, 2004
    
  
    Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
    
  
    Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
    
  
  2003
    IEEE J. Solid State Circuits, 2003
    
  
    Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
    
  
  2002
    Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
    
  
  2001
Implementation of a CMOS LNA plus mixer for GPS applications with no external components.
    
  
    IEEE Trans. Very Large Scale Integr. Syst., 2001
    
  
    IEEE J. Solid State Circuits, 2001
    
  
  2000
    IEEE J. Solid State Circuits, 2000
    
  
    Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
    
  
    Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
    
  
    Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
    
  
  1999
    Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
    
  
  1998
    IEEE Trans. Instrum. Meas., 1998
    
  
    IEEE Trans. Instrum. Meas., 1998
    
  
  1993
A BiCMOS Tunable Shaper for Detectors of Elementary Particles.
  
    Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993