Jiliang Zhang

Orcid: 0000-0001-8712-2964

Affiliations:
  • Hunan University, College of Computer Science and Electronic Engineering, Changsha, China
  • Northeastern University, Software College, Shenyang, China (2015 - 2017)
  • Hunan University, Changsha, China (PhD 2015)
  • University of Maryland at College Park, MD, USA (2013 - 2014)


According to our database1, Jiliang Zhang authored at least 99 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2024
SI PUF: An SRAM and Inverter-Based PUF With a Bit Error Rate of 0.0053% and 0.073/0.042 pJ/bit.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

An RRAM-Based Computing-in-Memory Architecture and Its Application in Accelerating Transformer Inference.
IEEE Trans. Very Large Scale Integr. Syst., March, 2024

Analog-in-Memory Accelerator Design Based on Memristive Arrays for Opposite Directional Interference Alignment Algorithm.
IEEE Trans. Ind. Informatics, March, 2024

A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing.
ACM Trans. Design Autom. Electr. Syst., January, 2024

Design and Application of Programmable Analog Circuit for Solving Lyapunov Matrix Equation Based on Memristors.
IEEE Trans. Ind. Electron., 2024

SegScope: Probing Fine-grained Interrupts via Architectural Footprints.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
FTMaster: A Detection and Mitigation System of Low-Rate Flow Table Overflow Attacks via SDN.
IEEE Trans. Netw. Serv. Manag., December, 2023

Mex+Sync: Software Covert Channels Exploiting Mutual Exclusion and Synchronization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Programmable In-memory Computing Circuit of Fast Hartley Transform.
ACM Trans. Design Autom. Electr. Syst., November, 2023

In-Memory Computing Circuit Implementation of Complex-Valued Hopfield Neural Network for Efficient Portrait Restoration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

Bionic Dual-Loop Emotional Learning Circuit and Its Application in Radiation Early Warning Monitoring.
IEEE Trans. Cogn. Dev. Syst., September, 2023

Design and Application of Biomimetic Memory Circuit Based on Hippocampus Mechanism.
IEEE Trans. Cogn. Dev. Syst., September, 2023

Programmable In-Memory Computing Circuit for Solving Combinatorial Matrix Operation in One Step.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

Circuit Design and Application of Discrete Cosine Transform Based on Memristor.
IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2023

PI PUF: A Processor-Intrinsic PUF for IoT.
Comput. Electr. Eng., January, 2023

GASF-IPP: Detection and Mitigation of LDoS Attack in SDN.
IEEE Trans. Serv. Comput., 2023

APMSA: Adversarial Perturbation Against Model Stealing Attacks.
IEEE Trans. Inf. Forensics Secur., 2023

Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications.
IEEE Trans. Emerg. Top. Comput., 2023

Artificial Intelligence Security: Threats and Countermeasures.
ACM Comput. Surv., 2023

SYNC+SYNC: Software Cache Write Covert Channels Exploiting Memory-disk Synchronization.
CoRR, 2023

SPECRUN: The Danger of Speculative Runahead Execution in Processors.
CoRR, 2023

A Fast Path Loss Model for Wireless Channels Considering Environmental Factors.
CoRR, 2023

Imperceptible Sample-Specific Backdoor to DNN with Denoising Autoencoder.
CoRR, 2023

A Ray-Launching Algorithm for Polarized Wireless Channel Prediction.
Proceedings of the IEEE Globecom Workshops 2023, 2023

Spoiler-Alert: Detecting Spoiler Attacks Using a Cuckoo Filter.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

MES-Attacks: Software-Controlled Covert Channels based on Mutual Exclusion and Synchronization.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

An FPGA-Compatible TRNG with Ultra-High Throughput and Energy Efficiency.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

PIMA-LPN: Processing-in-memory Acceleration for Efficient LPN-based Post-Quantum Cryptography.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

A Survey on Fault-Tolerance Methods for SRAM-Based FPGAs in Radiation Environments.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Message from the Chairs.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

A Comparison Study of the Compatibility Approaches for SGX Enclaves.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Processor based Intrinsic PUF Design for Approximate Computing: Faith or Reality?
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

2022
CRAlert: Hardware-Assisted Code Reuse Attack Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Lightweight and Machine-Learning-Resistant PUF Using Obfuscation-Feedback-Shift-Register.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Voltage Over-Scaling-Based Lightweight Authentication for IoT Security.
IEEE Trans. Computers, 2022

STT-MRAM-Based Reliable Weak PUF.
IEEE Trans. Computers, 2022

CT PUF: Configurable Tristate PUF Against Machine Learning Attacks for IoT Security.
IEEE Internet Things J., 2022

DA PUF: dual-state analog PUF.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Lightweight and Secure Branch Predictors against Spectre Attacks.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Adversarial Hardware With Functional and Topological Camouflage.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Set-Based Obfuscation for Strong PUFs Against Machine Learning Attacks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Security Enhancements for Approximate Machine Learning.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Unpaired Image-to-Image Translation Network for Semantic-based Face Adversarial Examples Generation.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Micro-architectural Cache Side-Channel Attacks and Countermeasures.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Adversarial Examples: Opportunities and Challenges.
IEEE Trans. Neural Networks Learn. Syst., 2020

Physical Unclonable Function-Based Key Sharing via Machine Learning for IoT Security.
IEEE Trans. Ind. Electron., 2020

Approximation Attacks on Strong PUFs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Backdoor Attacks and Countermeasures on Deep Learning: A Comprehensive Review.
CoRR, 2020

SIAT: A Systematic Inter-Component Communication Analysis Technology for Detecting Threats on Android.
CoRR, 2020

A novel method for malware detection on ML-based visualization technique.
Comput. Secur., 2020

Rethinking FPGA Security in the New Era of Artificial Intelligence.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

CT PUF: Configurable Tristate PUF against Machine Learning Attacks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Adversarial Audio: A New Information Hiding Method.
Proceedings of the Interspeech 2020, 2020

Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Privacy Threats and Protection in Machine Learning.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

HRAE: Hardware-assisted Randomization against Adversarial Example Attacks.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

Survey: Hardware Trojan Detection for Netlist.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

A Unified Formal Model for Proving Security and Reliability Properties.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
Recent Attacks and Defenses on FPGA-based Systems.
ACM Trans. Reconfigurable Technol. Syst., 2019

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

HCIC: Hardware-Assisted Control-Flow Integrity Checking.
IEEE Internet Things J., 2019

DeepCheck: A Non-intrusive Control-flow Integrity Checking based on Deep Learning.
CoRR, 2019

Adversarial Audio: A New Information Hiding Method and Backdoor for DNN-based Speech Recognition Models.
CoRR, 2019

ATMPA: attacking machine learning-based malware visualization detection methods via adversarial examples.
Proceedings of the International Symposium on Quality of Service, 2019

2018
Frequency Offset-Based Ring Oscillator Physical Unclonable Function.
IEEE Trans. Multi Scale Comput. Syst., 2018

Control Flow Integrity Based on Lightweight Encryption Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Adversarial Examples: Opportunities and Challenges.
CoRR, 2018

Adversarial Examples: Attacks on Machine Learning-based Malware Visualization Detection Methods.
CoRR, 2018

Crossover RO PUF-based Key Sharing for IoT Security.
CoRR, 2018

Machine Learning Attack and Defense on Voltage Over-scaling-based Lightweight Authentication.
CoRR, 2018

CMOS: Dynamic Multi-key Obfuscation Structure for Strong PUFs.
CoRR, 2018

HCIC: Hardware-assisted Control-flow Integrity Checking.
CoRR, 2018

T2FA: Transparent Two-Factor Authentication.
IEEE Access, 2018

Machine Learning Attacks on Voltage Over-scaling-based Lightweight Authentication.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017
A High Capacity Spatial Domain Data Hiding Scheme for Medical Images.
J. Signal Process. Syst., 2017

Publicly Verifiable Watermarking for Intellectual Property Protection in FPGA Design.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Enhancing Security of FPGA-Based Embedded Systems with Combinational Logic Binding.
J. Comput. Sci. Technol., 2017

Crossover Ring Oscillator PUF.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016
A Practical Logic Obfuscation Technique for Hardware Security.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Rebuttal to "Comments on 'A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing"'.
IEEE Trans. Inf. Forensics Secur., 2016

A new zero value attack combined fault sensitivity analysis on masked AES.
Microprocess. Microsystems, 2016

Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function.
J. Comput. Sci. Technol., 2016

A survey of hardware Trojan threat and defense.
Integr., 2016

Combinational Logic Binding for FPGA System Security.
Proceedings of the 2016 IEEE Trustcom/BigDataSE/ISPA, 2016

Physical unclonable functions-based linear encryption against code reuse attacks.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Reconfigurable Binding against FPGA Replay Attacks.
ACM Trans. Design Autom. Electr. Syst., 2015

A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing.
IEEE Trans. Inf. Forensics Secur., 2015

Application of Linear Predictive Coding for Doppler Through-Wall Radar Target Tracking.
IEEE Geosci. Remote. Sens. Lett., 2015

A Survey of Hardware Trojan Detection, Diagnosis and Prevention.
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

Reliable and Anti-cloning PUFs Based on Configurable Ring Oscillators.
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

2014
A Survey on Silicon PUFs and Recent Advances in Ring Oscillator PUFs.
J. Comput. Sci. Technol., 2014

A survey on security and trust of FPGA-based systems.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Improving the reliability of RO PUF using frequency offset.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

2013
FPGA IP protection by binding Finite State Machine to Physical Unclonable Function.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Design and Implementation of a Delay-Based PUF for FPGA IP Protection.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

2012
TimFastPlace: Critical-path based timing driven FastPlace.
IEICE Electron. Express, 2012

Efficient verification of IP watermarks in FPGA designs through lookup table content extracting.
IEICE Electron. Express, 2012


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