Taewhan Kim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2025

Invited: Physical Design Challenges for Design Technology Co-optimization.

[BibT_eX]

[DOI]

Proceedings of the 2025 International Symposium on Physical Design, 2025

PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation.

[BibT_eX]

[DOI]

Eunsol Jeong

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction for Designs in Advanced Technology Nodes With Consolidated Practical Applicability and Sustainability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024

Recap of the 29th Edition of the Asia and South Pacific Design Automation Conference (ASPDAC 2024).

[BibT_eX]

[DOI]

IEEE Des. Test, June, 2024

Enhancing Design Qualities Utilizing Multibit Flip-Flops: A Design and Technology Co-Optimization Driven Approach.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement.

[BibT_eX]

[DOI]

Kyeonghyeon Baek

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024

Placement legalization for heterogeneous cells of non-integer multiple-heights.

[BibT_eX]

[DOI]

Integr., 2024

Pre-route timing prediction and optimization with graph neural network models.

[BibT_eX]

[DOI]

Kyungjoon Chang

Integr., 2024

Improving Timing Quality Through Net Topology Optimization in Global Routing.

[BibT_eX]

[DOI]

Jayoung Yang

Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

Design and Allocation of Multi-bit Flip-flop Cells Amenable to Placement Legalization in Physical Design.

[BibT_eX]

[DOI]

Yeongyeong Shin

Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

Recent Research in Design and Technology Co-Optimization with Multi-Bit Flip-Flops.

[BibT_eX]

[DOI]

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction Model.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

Net Topology Exploration and Tuning for Mitigating Congestion in Global Routing.

[BibT_eX]

[DOI]

Hwapyong Kim

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Optimal Transistor Folding and Placement for Synthesizing Standard Cells of Complementary FET Technology.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Binding Multi-bit Flip-flop Cells through Design and Technology Co-optimization.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Eliminating Minimum Implant Area Violations With Design Quality Preservation.

[BibT_eX]

[DOI]

Eunsol Jeong

IEEE Trans. Very Large Scale Integr. Syst., May, 2023

Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew Scheduling.

[BibT_eX]

[DOI]

Jaewan Yang

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Challenges on Design and Technology Co-Optimization: Design Automation Perspective.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Maximizing Power Saving Through State-Driven Clock Gating.

[BibT_eX]

[DOI]

Chaehyun Kim

Proceedings of the 20th International SoC Design Conference, 2023

Allocation of Multi-bit Flip-Flops Targeting Low-Power Chips.

[BibT_eX]

[DOI]

Jinmyoung Kim

Proceedings of the 20th International SoC Design Conference, 2023

Fast Refinement on Placement Legalization for Designs with Mixed-Height Cells.

[BibT_eX]

[DOI]

Kihwan Jeon

Proceedings of the 20th International SoC Design Conference, 2023

Optimizing Timing for Multi-bit Flip-Flop Intensive Designs Compatible with Commercial EDA Flow.

[BibT_eX]

[DOI]

Ilseon Ha

Proceedings of the 20th International SoC Design Conference, 2023

Machine Learning Driven Synthesis of Clock Gating.

[BibT_eX]

[DOI]

Doyeon Won

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating.

[BibT_eX]

[DOI]

Sora Park

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool.

[BibT_eX]

[DOI]

Hwapyong Kim

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Deeper Weight Pruning Without Accuracy Loss in Deep Neural Networks: Signed-Digit Representation-Based Approach.

[BibT_eX]

[DOI]

Byungmin Ahn

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Speeding-up neuromorphic computation for neural networks: Structure optimization approach.

[BibT_eX]

[DOI]

Integr., 2022

ECO routing based on network flow method.

[BibT_eX]

[DOI]

Sehyeon Chung

Integr., 2022

Analysis of Impacting Multi-stack Standard Cells on Chip Implementation.

[BibT_eX]

[DOI]

Kyungjoon Chang

Proceedings of the 19th International SoC Design Conference, 2022

Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis.

[BibT_eX]

[DOI]

Sehyeon Chung

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

Improving Pin Accessibility of Standard Cells Through Fin Depopulation.

[BibT_eX]

[DOI]

Doyeon Won

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Selective Clock Gating Based on Comprehensive Power Saving Analysis.

[BibT_eX]

[DOI]

Sora Park

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Optimizing Timing in Placement Through I/O Signal Flipping on Multi-bit Flip-flops.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Design and Technology Co-Optimization Utilizing Multi-Bit Flip-Flop Cells.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Pin Accessibility-driven Placement Optimization with Accurate and Comprehensive Prediction Model.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A Systematic Removal of Minimum Implant Area Violations under Timing Constraint.

[BibT_eX]

[DOI]

Eunsol Jeong

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach.

[BibT_eX]

[DOI]

Taehwan Kim

IEEE Trans. Very Large Scale Integr. Syst., 2021

Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Allocation of Multibit Retention Flip-Flops for Power Gated Circuits: Algorithm-Design Unified Approach.

[BibT_eX]

[DOI]

Gyoung-Hwan Hyun

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Common Kernels and Convolutions in Binary- and Ternary-Weight Neural Networks.

[BibT_eX]

[DOI]

Byungmin Ahn

J. Circuits Syst. Comput., 2021

Practical Approach to Cell Replacement for Resolving Pin Inaccessibility.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Utilizing Middle-of-Line Resource in Filler Cells for Fixing Routing Failures.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Minimally Allocating Always-on State Retention Storage for Supporting Power Gating Circuits.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops.

[BibT_eX]

[DOI]

Jaejoon Yoon

Sehyeon Chung

Proceedings of the 18th International SoC Design Conference, 2021

Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis.

[BibT_eX]

[DOI]

Kyeongrok Jo

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis.

[BibT_eX]

[DOI]

Kyeonghyeon Baek

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Speeding up MUX-FSM based Stochastic Computing for On-device Neural Networks.

[BibT_eX]

[DOI]

Jongsung Kang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Boosting Pin Accessibility Through Cell Layout Topology Diversification.

[BibT_eX]

[DOI]

Kyeongrok Jo

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage.

[BibT_eX]

[DOI]

Integr., 2020

Steady state driven power gating for lightening always-on state retention storage.

[BibT_eX]

[DOI]

Taehwan Kim

Gyoung-Hwan Hyun

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Hybrid asynchronous circuit generation amenable to conventional EDA flow.

[BibT_eX]

[DOI]

Integr., 2019

SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018

Design and algorithm for clock gating and flip-flop co-optimization.

[BibT_eX]

[DOI]

Giyoung Yang

Proceedings of the International Conference on Computer-Aided Design, 2018

Structure optimizations of neuromorphic computing architectures for deep neural network.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling.

[BibT_eX]

[DOI]

Juyeon Kim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Clock buffer polarity assignment under useful skew constraints.

[BibT_eX]

[DOI]

Integr., 2017

2016

Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling.

[BibT_eX]

[DOI]

Seyong Ahn

Marios C. Papaefthymiou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes.

[BibT_eX]

[DOI]

Juyeon Kim

Integr., 2016

Synthesizing Asynchronous Circuits toward Practical Use.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Allocation of multi-bit flip-flops in logic synthesis for power optimization.

[BibT_eX]

[DOI]

Dongyoun Yi

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Clock buffer polarity assignment utilizing useful clock skews for power noise reduction.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Synthesis of TSV Fault-Tolerant 3-D Clock Trees.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing.

[BibT_eX]

[DOI]

Hyungjung Seo

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Synthesis for Power-Aware Clock Spines.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling.

[BibT_eX]

[DOI]

Seyong Ahn

Marios C. Papaefthymiou

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Integrated Resource Allocation and Binding in Clock Mesh Synthesis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2014

A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs.

[BibT_eX]

[DOI]

Kitae Park

Geunho Kim

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs.

[BibT_eX]

[DOI]

Kyoung-Hwan Lim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Tutorial: Methodology for designing reliable clock networks.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem.

[BibT_eX]

[DOI]

Juyeon Kim

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Power Saving by Task-Level Dynamic Voltage Scaling.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint.

[BibT_eX]

[DOI]

YongHwan Kim

Sanghoon Kwak

ACM Trans. Design Autom. Electr. Syst., 2012

Design Methodologies for Reliable Clock Networks.

[BibT_eX]

[DOI]

J. Comput. Sci. Eng., 2012

2011

Clock Tree synthesis for TSV-based 3D IC designs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2011

Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization.

[BibT_eX]

[DOI]

Hochang Jang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Clock design techniques considering circuit reliability.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2011

WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

Task-Level Dynamic Voltage Scaling for Embedded System Design: Recent Theoretical Results.

[BibT_eX]

[DOI]

J. Comput. Sci. Eng., 2010

Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew.

[BibT_eX]

[DOI]

Proceedings of the International Green Computing Conference 2010, 2010

Clock tree synthesis with pre-bond testability for 3D stacked IC designs.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Clock tree embedding for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Thermal sensor allocation and placement for reconfigurable systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Thermal-Aware High-Level Synthesis Based on Network Flow Method.

[BibT_eX]

[DOI]

Pilok Lim

J. Circuits Syst. Comput., 2009

Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization.

[BibT_eX]

[DOI]

Hochang Jang

Proceedings of the 46th Design Automation Conference, 2009

2007

Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization.

[BibT_eX]

[DOI]

Jungeun Kim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

Resource Sharing Combined with Layout Effects in High-Level Synthesis.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2006

A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications.

[BibT_eX]

[DOI]

Young-Jun Kim

J. VLSI Signal Process., 2006

Memory Access Driven Storage Assignment for Variables in Embedded System Design.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2006

Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006

HW/SW partitioning techniques for multi-mode multi-task embedded applications.

[BibT_eX]

[DOI]

Young-Jun Kim

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

A systematic IP and bus subsystem modeling for platform-based system design.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Thermal-aware high-level synthesis based on network flow method.

[BibT_eX]

[DOI]

Pilok Lim

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005

Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design.

[BibT_eX]

[DOI]

Hwansoo Han

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design.

[BibT_eX]

[DOI]

Jungeun Kim

Proceedings of the 42nd Design Automation Conference, 2005

2004

Tight integration of timing-driven synthesis and placement of parallel multiplier circuits.

[BibT_eX]

[DOI]

Keoncheol Shin

IEEE Trans. Very Large Scale Integr. Syst., 2004

Coupling-aware high-level interconnect synthesis [IC layout].

[BibT_eX]

[DOI]

Ki-Wook Kim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.

[BibT_eX]

[DOI]

Nak-Woong Eum

Chong-Min Kyung

IEEE Trans. Computers, 2004

Leakage power minimization for the synthesis of parallel multiplier circuits.

[BibT_eX]

[DOI]

Keoncheol Shin

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Profile-based optimal intra-task voltage scheduling for hard real-time applications.

[BibT_eX]

[DOI]

Jaewon Seo

Proceedings of the 41th Design Automation Conference, 2004

Memory access scheduling and binding considering energy minimization in multi-bank memory systems.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

An integrated approach to timing-driven synthesis and placement of arithmetic circuits.

[BibT_eX]

[DOI]

Keoncheol Shin

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Resource-constrained low-power bus encoding with crosstalk delay elimination.

[BibT_eX]

[DOI]

Meeyoung Cha

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

High-level synthesis for low power based on network flow method.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Minimum delay optimization for domino circuits - a coupling-aware approach.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2003

Synthesis of arithmetic circuits considering layout effects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Address assignment in DSP code generation - an integrated approach.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

An efficient inverse multiplier/divider architecture for cryptography systems.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

Synthesis and Optimization of Combinational Interface Circuits.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2002

Logic transformation for low-power synthesis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2002

Domino logic synthesis based on implication graph.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A Complete Model for Glitch Analysis in Logic Circuits.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2002

Binding Algorithm for Power Optimization Based on Network Flow Method.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2002

Enhanced bus invert encodings for low-power.

[BibT_eX]

[DOI]

Unni Narayanan

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Address code optimization using code scheduling for digital signal processors.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

An efficient low-power binding algorithm in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Layout-driven resource sharing in high-level synthesis.

[BibT_eX]

[DOI]

Jae-Hoon Kim

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Coupling-aware high-level interconnect synthesis for low power.

[BibT_eX]

[DOI]

Ki-Wook Kim

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Layout-aware synthesis of arithmetic circuits.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

Address assignment combined with scheduling in DSP code generation.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

G-vector: A New Model for Glitch Analysis in Logic Circuits.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2001

An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2001

An Integrated Data Path Optimization for Low Power Based on Network Flow Method.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.

[BibT_eX]

[DOI]

Nak-Woong Eum

Chong-Min Kyung

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

An accurate evaluation of routing density for symmetrical FPGAs.

[BibT_eX]

[DOI]

Nak-Woong Eum

Chong-Min Kyung

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

A Static Estimation Technique of Power Sensitivity in Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders.

[BibT_eX]

[DOI]

Youngtae Kim

Proceedings of ASP-DAC 2001, 2001

2000

An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization.

[BibT_eX]

[DOI]

Chaeryung Park

VLSI Design, 2000

A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders.

[BibT_eX]

[DOI]

Youngtae Kim

J. Circuits Syst. Comput., 2000

Decomposition of Bus-Invert Coding for Low-Power I/O.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2000

Behavioral-level partitioning for low power design in control-dominated application.

[BibT_eX]

[DOI]

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper).

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

Optimal allocation of carry-save-adders in arithmetic optimization.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998

[BibT_eX]

[DOI]

Chaeryung Park

J. VLSI Signal Process., 1998

Circuit optimization using carry-save-adder cells.

[BibT_eX]

[DOI]

William Jao

Steven W. K. Tjiang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Arithmetic Optimization Using Carry-Save-Adders.

[BibT_eX]

[DOI]

William Jao

Steven W. K. Tjiang

Proceedings of the 35th Conference on Design Automation, 1998

1996

An integrated algorithm for incremental data path synthesis.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1996

1995

A new approach to the multiport memory allocation problem in data path synthesis.

[BibT_eX]

[DOI]

Integr., 1995

1994

A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability.

[BibT_eX]

[DOI]

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

[BibT_eX]

[DOI]

Chaeryung Park

Proceedings of the European Design Automation Conference 1993, 1993

Utilization of Multiport Memories in Data Path Synthesis.

[BibT_eX]

[DOI]