V. Kamakoti

According to our database1, V. Kamakoti authored at least 126 papers between 1992 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips.
IET Comput. Digit. Tech., 2020

Net-Police: A network patrolling service for effective mitigation of volumetric DDoS attacks.
Comput. Commun., 2020

Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER.
IEEE Comput. Archit. Lett., 2020

Depending on HTTP/2 for Privacy? Good Luck!
Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2020

Sparsity-Aware Caches to Accelerate Deep Neural Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

VNF-DOC: A Dynamic Overload Controller for Virtualized Network Functions in Cloud.
Proceedings of the Advanced Information Networking and Applications, 2020

2019
PROLEMus: A Proactive Learning-Based MAC Protocol Against PUEA and SSDF Attacks in Energy Constrained Cognitive Radio Networks.
IEEE Trans. Cogn. Commun. Netw., 2019

PERI: A Posit Enabled RISC-V Core.
CoRR, 2019

White Mirror: Leaking Sensitive Information from Interactive Netflix Movies using Encrypted Traffic Analysis.
Proceedings of the ACM SIGCOMM 2019 Conference Posters and Demos, 2019

SHAKTI-MS: a RISC-V processor for memory safety in C.
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019

Towards Measuring Quality of Service in Untrusted Multi-Vendor Service Function Chains: Balancing Security and Resource Consumption.
Proceedings of the 2019 IEEE Conference on Computer Communications, 2019

Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection.
Proceedings of the International Conference on Computer-Aided Design, 2019

Towards Identifying Early Indicators of a Malware Infection.
Proceedings of the 2019 ACM Asia Conference on Computer and Communications Security, 2019

2018
MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis.
J. Low Power Electron., 2018

An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators.
ACM J. Emerg. Technol. Comput. Syst., 2018

GANDALF: A Fine-Grained Hardware-Software Co-Design for Preventing Memory Attacks.
IEEE Embed. Syst. Lett., 2018

ApproxBC: Blockchain Design Alternatives for Approximation-Tolerant Resource-Constrained Applications.
IEEE Commun. Stand. Mag., 2018

2017
Approximate Error Detection With Stochastic Checkers.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Optimal Don't Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing.
ACM Trans. Design Autom. Electr. Syst., 2017

A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Shakti-T: A RISC-V Processor with Light Weight Security Extensions.
Proceedings of the Hardware and Architectural Support for Security and Privacy, 2017

A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
Power Consumption versus Hardware Security: Feasibility Study of Differential Power Attack on Linear Feedback Shift Register Based Stream Ciphers and Its Countermeasures.
J. Low Power Electron., 2016

ProMAC: A proactive model predictive control based MAC protocol for cognitive radio vehicular networks.
Comput. Commun., 2016

SHAKTI Processors: An Open-Source Hardware Initiative.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Component fault localization using switching current measurements.
Proceedings of the 21th IEEE European Test Symposium, 2016

2015
DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing.
ACM Trans. Design Autom. Electr. Syst., 2015

Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications.
J. Low Power Electron., 2015

ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors.
ACM J. Emerg. Technol. Comput. Syst., 2015

Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization.
Appl. Soft Comput., 2015

Framework for Selective Flip-Flop Replacement for Soft Error Mitigation.
Proceedings of the 28th International Conference on VLSI Design, 2015

DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

SHAKTI-F: A Fault Tolerant Microprocessor Architecture.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
XStat: Statistical <i>X</i>-Filling Algorithm for Peak Capture Power Reduction in Scan Tests.
J. Low Power Electron., 2014

ReMap: A Novel Automated Peephole Optimization Based Approach for Logic, Delay and Power Minimization.
J. Low Power Electron., 2014

ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

2013
An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test.
J. Low Power Electron., 2013

Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions.
J. Low Power Electron., 2013

A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays.
ACM J. Emerg. Technol. Comput. Syst., 2013

A syllable based statistical text to speech system.
Proceedings of the 21st European Signal Processing Conference, 2013

PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information.
Proceedings of the 18th IEEE European Test Symposium, 2013

Using timers to switch-off TCAM banks in routers.
Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2013

2012
Interconnect Aware Test Power Reduction.
J. Low Power Electron., 2012

Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs.
J. Low Power Electron., 2012

A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands.
J. Electr. Comput. Eng., 2012

The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency.
Proceedings of the 2012 Workshop on Power-Aware Computing Systems, HotPower'12, 2012

2011
ROSY: recovering processor and memory systems from hard errors.
ACM SIGOPS Oper. Syst. Rev., 2011

Hardware based genetic evolution of self-adaptive arbitrary response FIR filters.
Appl. Soft Comput., 2011

Post-Synthesis Circuit Techniques for Runtime Leakage Reduction.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Simulation Based Buffer Sizing Algorithm for Network on Chips.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Method for Integrating Network-on-Chip Topologies with 3D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Towards Quick Solutions for Generalized Placement Problem.
Proceedings of the International Symposium on Electronic System Design, 2011

Reconstructing Hardware Transactional Memory for Workload Optimized Systems.
Proceedings of the Advanced Parallel Processing Technologies - 9th International Symposium, 2011

2010
Constructing Online Testable Circuits Using Reversible Logic.
IEEE Trans. Instrum. Meas., 2010

Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation.
IEEE Trans. Broadcast., 2010

Impact of Temperature on Test Quality.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009
HTM design spaces: complete decoupling from caches and achieving highly concurrent transactions.
ACM SIGOPS Oper. Syst. Rev., 2009

Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits.
J. Low Power Electron., 2009

Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures.
J. Low Power Electron., 2009

Efficient Grouping of Fail Chips for Volume Yield Diagnostics.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008
Automatic Constraint Based Test Generation for Behavioral HDL Models.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction.
J. Low Power Electron., 2008

2007
System-on-programmable-chip implementation for on-line face recognition.
Pattern Recognit. Lett., 2007

Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits.
J. Low Power Electron., 2007

Variation-Tolerant, Power-Safe Pattern Generation.
IEEE Des. Test Comput., 2007

A novel approach to the placement and routing problems for field programmable gate arrays.
Appl. Soft Comput., 2007

Power Virus Generation Using Behavioral Models of Circuits.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Controllability-driven Power Virus Generation for Digital Circuits.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test.
Proceedings of the 2007 IEEE International Test Conference, 2007

A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test.
Proceedings of the 2007 IEEE International Test Conference, 2007

LFSR Based Stream Ciphers Are Vulnerable to Power Attacks.
Proceedings of the Progress in Cryptology, 2007

Interactive presentation: On power-profiling and pattern generation for power-safe scan tests.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses.
J. Low Power Electron., 2006

On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores.
J. Low Power Electron., 2006

Ultra Folded High-Speed Architectures for Reed-Solomon Decoders.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Delay and peak power minimization for on-chip buses using temporal redundancy.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005
Pseudo-online testing methodologies for various components of field programmable gate arrays.
Microprocess. Microsystems, 2005

Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

FPGA based Agile Algorithm-On-Demand Co-Processor.
Proceedings of the 2005 Design, 2005

A Framework for Automatic Assembly Program Generator (A<sup>2</sup>PG) for Verification and Testing of Processor Cores.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A function generator-based reconfigurable system.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A Bus Encoding Technique for Power and Cross-talk Minimization.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

An Evolutionary Algorithm for Automatic Spatial Partitioning in Reconfigurable Environments.
Proceedings of the MICAI 2004: Advances in Artificial Intelligence, 2004

MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

An Architecture for Real Time Face Recognition Using WMPCA.
Proceedings of the ICVGIP 2004, 2004

A Hardware-Directed Face Recognition System Based on Local Eigen-analysis with PCNN.
Proceedings of the Neural Information Processing, 11th International Conference, 2004

Face Recognition Using Weighted Modular Principle Component Analysis.
Proceedings of the Neural Information Processing, 11th International Conference, 2004

A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks.
Proceedings of the Field Programmable Logic and Application, 2004

SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis.
Proceedings of the 2004 Design, 2004

2003
On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems.
Proceedings of the International Conference on VLSI, 2003

Dynamic Coding Technique For Low-Power Data Bus.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments.
Proceedings of the 1st Indian International Conference on Artificial Intelligence, 2003

Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification.
Proceedings of the High Performance Computing - HiPC 2003, 10th International Conference, 2003

Testable Clock Routing Architecture for Field Programmable Gate Arrays.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
A novel three phase parallel genetic approach to routing for field programmable gate arrays.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

2001
Toward Optimal Player Weights in Secure Distributed Protocols.
Proceedings of the Progress in Cryptology, 2001

1999
Adaptive finite element analysis on a parallel and distributed environment.
Parallel Comput., 1999

1998
An Optimal Algorithm for Computing Vissible Nearest Foreign Neighbors Among Colored Line Segments.
Proceedings of the Algorithm Theory, 1998

Reducing Simple Polygons to Triangles - A Proof for an Improved Conjecture.
Proceedings of the Automata, Languages and Programming, 25th International Colloquium, 1998

The Colored Sector Search Tree: A Dynamic Data Structure for Efficient High Dimensional Nearest-Foreign-Neighbor Queries.
Proceedings of the Computing and Combinatorics, 4th Annual International Conference, 1998

1997
Sparse Dominance Queries for Many Points in Optimal Time and Space.
Inf. Process. Lett., 1997

Efficient Algorithms for Prefix and General Prefix Computations on Distributed Shared Memory Systems with Applications.
Proceedings of the 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 1997

An optimal parallel algorithm for the all-nearest-foreign-neighbors problem in arbitrary dimensions.
Proceedings of the Fourth International on High-Performance Computing, 1997

1995
An Efficient Randomized Algorithm for the Closest Pair Problem on Colored Point Sets.
Nord. J. Comput., 1995

Efficient Parallel Algorithms for Permutation Graphs.
J. Parallel Distributed Comput., 1995

Efficient Randomized Incremental Algorithm For The Closest Pair Problem Using Leafary Trees.
Proceedings of the Computing and Combinatorics, First Annual International Conference, 1995

1994
Efficient Randomized Parallel Algorithm for the Closest Pair Problem in D-dimension.
Proceedings of the Technology and Foundations - Information Processing '94, Volume 1, Proceedings of the IFIP 13th World Computer Congress, Hamburg, Germany, 28 August, 1994

1992
An Optimal Algorithm for Reconstructing a Binary Tree.
Inf. Process. Lett., 1992


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