Zheyu Yan
Orcid: 0000-0003-1830-606X
According to our database1,
Zheyu Yan
authored at least 37 papers
between 2020 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
SenHDC: A 3-D NAND Flash-Based Processing-in-Sensor Hyperdimensional Computing Architecture.
IEEE Trans. Very Large Scale Integr. Syst., July, 2025
FactorHD: A Hyperdimensional Computing Model for Multi-Object Multi-Class Representation and Factorization.
CoRR, July, 2025
CSA-CiM: Enhancing Multifunctional Computing-in-Memory With Configurable Sense Amplifiers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2025
ANAS: Software-hardware co-design of approximate neural network accelerators via neural architecture search.
Integr., 2025
Proceedings of the Design, Automation & Test in Europe Conference, 2025
Algorithm-Hardware Co-Design of a Unified Accelerator for Non-Linear Functions in Transformers.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
A 10.60 μW 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
Invited Paper: Boosting Standard Cell Library Characterization with Machine Learning.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
Compute-in-Memory-Based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024
U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2024
FRCSyn-onGoing: Benchmarking and comprehensive evaluation of real and synthetic data to improve face recognition systems.
Inf. Fusion, 2024
Tiny-Align: Bridging Automatic Speech Recognition and Large Language Model on the Edge.
CoRR, 2024
Rethinking Medical Anomaly Detection in Brain MRI: An Image Quality Assessment Perspective.
CoRR, 2024
CoRR, 2024
Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architectures.
CoRR, 2024
FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models.
CoRR, 2024
FRCSyn Challenge at WACV 2024: Face Recognition Challenge in the Era of Synthetic Data.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision Workshops, 2024
Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architectures.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024
Special Session: Sustainable Deployment of Deep Neural Networks on Non-Volatile Compute-in-Memory Accelerators.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2024
Proceedings of the Biometric Recognition - 18th Chinese Conference, 2024
FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models : (Invited Paper).
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
Negative Feedback Training: A Novel Concept to Improve Robustness of NVCiM DNN Accelerators.
CoRR, 2023
On the Viability of Using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators Through Training with Right-Censored Gaussian Noise.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
2022
VisualNet: An End-to-End Human Visual System Inspired Framework to Reduce Inference Latency of Deep Neural Networks.
IEEE Trans. Computers, 2022
CoRR, 2022
A Semi-Decoupled Approach to Fast and Optimal Hardware-Software Co-Design of Neural Accelerators.
CoRR, 2022
Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators.
IEEE Trans. Computers, 2021
Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020