Masaaki Higashitani

According to our database, Masaaki Higashitani authored at least 17 papers between 1991 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Low Cost 'On Pitch Select Gate' (OPS) Technology for 3D Flash Memory.

Abhijith Prakash, Xiang Yang, James Kai, Xiaochen Zhu, Henry Chin, Guirong Liang, Deepanshu Dutta, Masaaki Higashitani, Kazuki Isozumi, Shinsuke Yada, Sayako Nagamine, Kenichi Okabe, Yutaka Ohira, Manabu Hayashi, Satoshi Shimizu, Hideto Tomiie, Takayuki Inoue, Shota Murai, Takeshi Sakaguchi, Youichi Minemura, Shoichi Miyazaki, Megumi Ishiduki, Yasuhiro Shiino, Shinji Suzuki

Proceedings of the IEEE International Memory Workshop, 2025

2014

A 130.7-mm² 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology.

Tz-Yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang, Takahiko Sasaki, Ali Al-Shamma, Chin-Yu Chen, Mayank Gupta, Greg Hilton, Achal Kathuria, Vincent Lai, Masahide Matsumoto, Anurag Nigam, Anil Pai, Jayesh Pakhale, Chang Hua Siau, Xiaoxia Wu, Yibo Yin, Nicolas Nagel, Yoichiro Tanaka, Masaaki Higashitani, Tim Minvielle, Chandu Gorla, Takayuki Tsukamoto, Takeshi Yamaguchi, Mutsumi Okajima, Takayuki Okamura, Satoru Takase, Hirofumi Inoue, Luca Fasoli

IEEE J. Solid State Circuits, 2014

2013

A 130.7mm² 2-layer 32Gb ReRAM memory device in 24nm technology.

Tz-Yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang, Takahiko Sasaki, Sravanti Addepalli, Ali Al-Shamma, Chin-Yu Chen, Mayank Gupta, Greg Hilton, Saurabh Joshi, Achal Kathuria, Vincent Lai, Deep Masiwal, Masahide Matsumoto, Anurag Nigam, Anil Pai, Jayesh Pakhale, Chang Hua Siau, Xiaoxia Wu, Ronald Yin, Liping Peng, Jang Yong Kang, Sharon Huynh, Huijuan Wang, Nicolas Nagel, Yoichiro Tanaka, Masaaki Higashitani, Tim Minvielle, Chandu Gorla, Takayuki Tsukamoto, Takeshi Yamaguchi, Mutsumi Okajima, Takayuki Okamura, Satoru Takase, Takahiko Hara, Hirofumi Inoue, Luca Fasoli, Mehrdad Mofidi, Ritu Shrivastava, Khandker Quader

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A 151-mm² 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology.

Koichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Jumpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Takeshi Ogawa, Toshiaki Edahiro, Makoto Iwai, Osamu Nagao, Junji Musha, Takatoshi Minamoto, Yuka Furuta, Kosuke Yanagidaira, Yuya Suzuki, Dai Nakamura, Yoshikazu Hosomura, Rieko Tanaka, Hiromitsu Komai, Mai Muramoto, Go Shikata, Ayako Yuminaka, Kiyofumi Sakurai, Manabu Sakai, Hong Ding, Mitsuyuki Watanabe, Yosuke Kato, Toru Miwa, Alex Mak, Masaru Nakamichi, Gertjan Hemink, Dana Lee, Masaaki Higashitani, Brian Murphy, Bo Lei, Yasuhiko Matsunaga, Kiyomi Naruke, Takahiko Hara

IEEE J. Solid State Circuits, 2012

A 19nm 112.8mm² 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface.

Noboru Shibata, Kazushige Kanda, Toshiki Hisada, Katsuaki Isobe, Manabu Sato, Yui Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, Kazuko Inuzuka, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, J. Nakai, Kiyoaki Iwasa, Masatsugu Kojima, Toshihiro Suzuki, Yuya Suzuki, Shintaro Sakai, Tomofumi Fujimura, Yuko Utsunomiya, Toshifumi Hashimoto, Makoto Miakashi, Naoki Kobayashi, M. Inagaki, Yuuki Matsumoto, Satoshi Inoue, Yoshinao Suzuki, D. He, Yasuhiko Honda, Junji Musha, Masaki Nakagawa, Mitsuaki Honma, Naofumi Abiko, Mitsumasa Koyanagi, Masahiro Yoshihara, Kazumi Ino, Mitsuhiro Noguchi, Teruhiko Kamei, Yosuke Kato, Shingo Zaitsu, Hiroaki Nasu, Takuya Ariki, Hardwell Chibvongodze, Mitsuyuki Watanabe, Hong Ding, Naoki Ookuma, Ryuji Yamashita, G. Liang, Gertjan Hemink, Farookh Moogat, Cuong Trinh, Masaaki Higashitani, Tuan Pham, Kousuke Kanazawa

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode.

Yan Li, Seungpil Lee, Ken Oowada, Hao Nguyen, Qui Nguyen, Nima Mokhlesi, Cynthia Hsu, Jason Li, Venky Ramachandra, Teruhiko Kamei, Masaaki Higashitani, Tuan Pham, Mitsuaki Honma, Yoshihisa Watanabe, Kazumi Ino, Binh Le, Byungki Woo, Khin Htoo, Taiyuan Tseng, Long Pham, Frank Tsai, Kwang-Ho Kim, Yi-Chieh Chen, Min She, Jonghak Yuh, Alex Chu, Chen Chen, Ruchi Puri, Hung-Szu Lin, Yi-Fang Chen, William Mak, Jonathan Huynh, Jim Chan, Mitsuyuki Watanabe, Daniel Yang, Grishma Shah, Pavithra Souriraj, Dinesh Tadepalli, Tenugu Suman, Ray Gao, Viski Popuri, Behdad Azarbayjani, Ravindra Madpur, James Lan, Emilio Yero, Feng Pan, Patrick Hong, Jang Yong Kang, Farookh Moogat, Yupin Fong, Raul Cernea, Sharon Huynh, Cuong Trinh, Mehrdad Mofidi, Ritu Shrivastava, Khandker Quader

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 151mm² 64Gb MLC NAND flash memory in 24nm CMOS technology.

Koichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Jumpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Toshiaki Edahiro, Takeshi Ogawa, Makoto Iwai, Osamu Nagao, Junji Musha, Takatoshi Minamoto, Kosuke Yanagidaira, Yuya Suzuki, Dai Nakamura, Yoshikazu Hosomura, Hiromitsu Komai, Yuka Furuta, Mai Muramoto, Rieko Tanaka, Go Shikata, Ayako Yuminaka, Kiyofumi Sakurai, Manabu Sakai, Hong Ding, Mitsuyuki Watanabe, Yosuke Kato, Toru Miwa, Alex Mak, Masaru Nakamichi, Gertjan Hemink, Dana Lee, Masaaki Higashitani, Brian Murphy, Bo Lei, Yasuhiko Matsunaga, Kiyomi Naruke, Takahiko Hara

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009

A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate.

Yan Li, Seungpil Lee, Yupin Fong, Feng Pan, Tien-Chien Kuo, Jongmin Park, Tapan Samaddar, Hao Nguyen, Man Mui, Khin Htoo, Teruhiko Kamei, Masaaki Higashitani, Emilio Yero, Gyuwan Kwon, Phil Kliza, Jun Wan, Tetsuya Kaneko, Hiroshi Maejima, Hitoshi Shiga, Makoto Hamada, Norihiro Fujita, Kazunori Kanebako, Eugene Tam, Anne Koh, Iris Lu, Calvin Chia-Hong Kuo, Trung Pham, Jonathan Huynh, Qui Nguyen, Hardwell Chibvongodze, Mitsuyuki Watanabe, Ken Oowada, Grishma Shah, Byungki Woo, Ray Gao, Jim Chan, James Lan, Patrick Hong, Liping Peng, Debi Das, Dhritiman Ghosh, Vivek Kalluru, Sanjay Kulkarni, Raul-Adrian Cernea, Sharon Huynh, Dimitris Pantelakis, Chi-Ming Wang, Khandker Quader

IEEE J. Solid State Circuits, 2009

A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology.

Raul Cernea, Long Pham, Farookh Moogat, Siu Lung Chan, Binh Le, Yan Li, Shouchang Tsao, Taiyuan Tseng, Khanh Nguyen, Jason Li, Jayson Hu, Jonghak Yuh, Cynthia Hsu, Fanglin Zhang, Teruhiko Kamei, Hiroaki Nasu, Phil Kliza, Khin Htoo, Jeffrey Lutze, Yingda Dong, Masaaki Higashitani, Junhui Yang, Hung-Szu Lin, Vamshi Sakhamuri, Alan Li, Feng Pan, Sridhar Yadala, Subodh Taigor, Kishan Pradhan, James Lan, Jim Chan, Takumi Abe, Yasuyuki Fukuda, Hideo Mukai, Koichi Kawakami, Connie Liang, Tommy Ip, Shu-Fen Chang, Jaggi Lakshmipathi, Sharon Huynh, Dimitris Pantelakis, Mehrdad Mofidi, Khandker Quader

IEEE J. Solid State Circuits, 2009

A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS.

Cuong Trinh, Noboru Shibata, Takeshi Nakano, Mikio Ogawa, Jumpei Sato, Yoshikazu Takeyama, Katsuaki Isobe, Binh Le, Farookh Moogat, Nima Mokhlesi, Kenji Kozakai, Patrick Hong, Teruhiko Kamei, Kiyoaki Iwasa, J. Nakai, Takahiro Shimizu, Mitsuaki Honma, Shintaro Sakai, Toshimasa Kawaai, Satoru Hoshi, Jonghak Yuh, Cynthia Hsu, Taiyuan Tseng, Jason Li, Jayson Hu, M. Liu, Shahzad Khalid, J. Chen, Mitsuyuki Watanabe, Hung-Szu Lin, Junhui Yang, K. McKay, Khanh Nguyen, Tuan Pham, Y. Matsuda, K. Nakamura, Kazunori Kanebako, Susumu Yoshikawa, W. Igarashi, Atsushi Inoue, T. Takahashi, Yukio Komatsu, C. Suzuki, Kousuke Kanazawa, Masaaki Higashitani, Seungpil Lee, T. Murai, K. Nguyen, James Lan, Sharon Huynh, Mark Murin, Mark Shlick, Menahem Lasser, Raul Cernea, Mehrdad Mofidi, K. Schuegraf, Khandker Quader

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate.

Yan Li, Seungpil Lee, Yupin Fong, Feng Pan, Tien-Chien Kuo, Jong Park, Tapan Samaddar, Hao Nguyen, Man Mui, Khin Htoo, Teruhiko Kamei, Masaaki Higashitani, Emilio Yero, Gyuwan Kwon, Phil Kliza, Jun Wan, Tetsuya Kaneko, Hiroshi Maejima, Hitoshi Shiga, Makoto Hamada, Norihiro Fujita, Kazunori Kanebako, Eugene Tam, Anne Koh, Iris Lu, Calvin Chia-Hong Kuo, Trung Pham, Jonathan Huynh, Qui Nguyen, Hardwell Chibvongodze, Mitsuyuki Watanabe, Ken Oowada, Grishma Shah, Byungki Woo, Ray Gao, Jim Chan, James Lan, Patrick Hong, Liping Peng, Debi Das, Dhritiman Ghosh, Vivek Kalluru, Sanjay Kulkarni, Raul Cernea, Sharon Huynh, Dimitris Pantelakis, Chi-Ming Wang, Khandker Quader

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 120mm² 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology.

Kazushige Kanda, Masaru Koyanagi, Toshio Yamamura, Koji Hosono, Masahiro Yoshihara, Toru Miwa, Yosuke Kato, Alex Mak, Siu Lung Chan, Frank Tsai, Raul Cernea, Binh Le, Eiichi Makino, Takashi Taira, Hiroyuki Otake, Norifumi Kajimura, Susumu Fujimura, Yoshiaki Takeuchi, Mikihiko Itoh, Masanobu Shirakawa, Dai Nakamura, Yuya Suzuki, Yuki Okukawa, Masatsugu Kojima, Kazuhide Yoneya, Takamichi Arizono, Toshiki Hisada, Shinji Miyamoto, Mitsuhiro Noguchi, Toshitake Yaegashi, Masaaki Higashitani, Fumitoshi Ito, Teruhiko Kamei, Gertjan Hemink, Tooru Maruyama, Kazumi Ino, Shigeo Ohshima

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm.

Raul Cernea, Long Pham, Farookh Moogat, Siu Lung Chan, Binh Le, Yan Li, Shouchang Tsao, Taiyuan Tseng, Khanh Nguyen, Jason Li, Jayson Hu, Jong Park, Cynthia Hsu, Fanglin Zhang, Teruhiko Kamei, Hiroaki Nasu, Phil Kliza, Khin Htoo, Jeffery Lutze, Yingda Dong, Masaaki Higashitani, Junhui Yang, Hung-Szu Lin, Vamshi Sakhamuri, Alan Li, Feng Pan, Sridhar Yadala, Subodh Taigor, Kishan Pradhan, James Lan, Jim Chan, Takumi Abe, Yasuyuki Fukuda, Hideo Mukai, Koichi Kawakami, Connie Liang, Tommy Ip, Shu-Fen Chang, Jaggi Lakshmipathi, Sharon Huynh, Dimitris Pantelakis, Mehrdad Mofidi, Khandker Quader

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

A 56-nm CMOS 99-mm² 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput.

Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa, Shigeo Ohshima

IEEE J. Solid State Circuits, 2007

2006

A 146-mm² 8-gb multi-level NAND flash memory with 70-nm CMOS technology.

Takahiko Hara, Koichi Fukuda, Kazuhisa Kanazawa, Noboru Shibata, Koji Hosono, Hiroshi Maejima, Michio Nakagawa, Takumi Abe, Masatsugu Kojima, Masaki Fujiu, Yoshiaki Takeuchi, Kazumi Amemiya, Midori Morooka, Teruhiko Kamei, Hiroaki Nasu, Chi-Ming Wang, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Tohru Maruyama, Susumu Yoshikawa, Masaaki Higashitani, Tuan D. Pham, Yupin Fong, Toshiharu Watanabe

IEEE J. Solid State Circuits, 2006

A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput.

Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa, Shigeo Ohshima

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

1991

A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture.

Masao Taguchi, Hiroyoshi Tomita, Toshiya Uchida, Yasuhiro Ohnishi, Kimiaki Sato, Taiji Ema, Masaaki Higashitani, Takashi Yabu

IEEE J. Solid State Circuits, November, 1991