Bich-Yen Nguyen

According to our database, Bich-Yen Nguyen authored at least 15 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Non-Destructive-Read 1T1C Ferroelectric Capacitive Memory Cell with BEOL 3D Monolithically Integrated IGZO Access Transistor for 4F² High-Density Integration.

Zuopu Zhou, Leming Jiao, Qiwen Kong, Zijie Zheng, Kaizhen Han, Yue Chen, Chen Sun, Bich-Yen Nguyen, Xiao Gong

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections.

A. Vandooren, N. Parihar, Jacopo Franco, Roger Loo, Hiroaki Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, Kevin Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, Andriy Hikavyy, Anne Jourdain, O. Mourey, G. Gaudin, S. Reboh, L. Le Van-Jodin, Guillaume Besnard, C. Roda Neve, Bich-Yen Nguyen, Iuliana P. Radu, E. Dentoni Litta, N. Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Smart Cut^™ technology: from Substrate Enginnering to Advanced 3D Integration.

Guillaume Besnard, Bich-Yen Nguyen, Christophe Maleville

Proceedings of the International Conference on IC Design and Technology, 2022

2019

Low Temperature SmartCutTM enables High Density 3D SoC Applications.

Walter Schwarzenbach, Bich-Yen Nguyen, Guillaume Besnard

Proceedings of the International Conference on IC Design and Technology, 2019

22FD-SOI Variability Improvement Thanks to SmartCut Thickness Control at Atomic Scale.

Walter Schwarzenbach, L. Loubriat, Vincent Joseph, Laurent Viravaux, Olivier Moreau, Sebastien Lasserre, Bich-Yen Nguyen

Proceedings of the 49th European Solid-State Device Research Conference, 2019

2018

Effect of measurement speed (μs-800 ps) on the characterization of reliability behaviors for FDSOI nMOSFETs.

Yiming Qu, Ran Cheng, Wei Liu, Junkang Li, Bich-Yen Nguyen, Olivier Faynot, Nuo Xu, Bing Chen, Yi Zhao

Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017

FD-SOI material enabling CMOS technology disruption from 65nm to 12nm and beyond.

Walter Schwarzenbach, Manuel Sellier, Bich-Yen Nguyen, Christophe Girard, Christophe Maleville

Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Layout engineering to suppress hysteresis of negative capacitance FinFET.

Eunah Ko, Jaesung Jo, Changhwan Shin, Bich-Yen Nguyen

Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

2015

3D monolithic integration: Stacking technology and applications.

Ionut Radu, Bich-Yen Nguyen, Gweltaz Gaudin, Carlos Mazure

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

2012

Strained silicon on insulator substrates for fully depleted application.

Walter Schwarzenbach, N. Daval, S. Kerdiles, G. Chabanne, C. Figuet, S. Guerroudj, O. Bonnin, X. Cauchy, Bich-Yen Nguyen, Christophe Maleville

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2010

32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit.

Olivier Thomas, Jean-Philippe Noel, Claire Fenouillet-Béranger, Marie-Anne Jaud, J. Dura, P. Perreau, Frédéric Boeuf, François Andrieu, D. Delprat, F. Boedt, Konstantin Bourdelle, Bich-Yen Nguyen, Andrei Vladimirescu, Amara Amara

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

SRAM design in fully-depleted SOI technology.

Borivoje Nikolic, Changhwan Shin, Min Hee Cho, Xin Sun, Tsu-Jae King Liu, Bich-Yen Nguyen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

FDSOI: From substrate to devices and circuit applications.

Carlos Mazure, Richard Ferrant, Bich-Yen Nguyen, Walter Schwarzenbach, Cécile Moulin

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below.

Claire Fenouillet-Béranger, P. Perreau, S. Denorme, L. Tosti, François Andrieu, Olivier Weber, S. Barnola, C. Arvet, Y. Campidelli, Sébastien Haendler, R. Beneyton, C. Perrot, C. de Buttet, P. Gros, L. Pham-Nguyen, F. Leverd, P. Gouraud, F. Abbate, F. Baron, A. Torres, C. Laviron, L. Pinzelli, J. Vetier, C. Borowiak, A. Margain, D. Delprat, F. Boedt, Konstantin Bourdelle, Bich-Yen Nguyen, Olivier Faynot, Thomas Skotnicki

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2005

Physics-based compact modeling for nonclassical CMOS.

Vishal P. Trivedi, Jerry G. Fossum, Leo Mathew, Murshed M. Chowdhury, Weimin Zhang, Glenn O. Workman, Bich-Yen Nguyen

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005