Olivier Thomas

According to our database1, Olivier Thomas authored at least 35 papers between 2001 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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On csauthors.net:

Bibliography

2021
Model order reduction methods for geometrically nonlinear structures: a review of nonlinear techniques.
CoRR, 2021

2020
A purely frequency based Floquet-Hill formulation for the efficient stability computation of periodic solutions of ordinary differential systems.
J. Comput. Phys., 2020

Non-intrusive reduced order modelling for the dynamics of geometrically nonlinear flat structures using three-dimensional finite elements.
CoRR, 2020

2019
A Novel Method for Accelerating the Analysis of Nonlinear Behaviour of Power Grids using Normal Form Technique.
Proceedings of the 2019 IEEE PES Innovative Smart Grid Technologies Europe, 2019

2016
Design considerations for reliable OxRAM-based non-volatile flip-flops in 28nm FD-SOI technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Thermo-mechanical characterization of passive stress sensors in Si interposer.
Microelectron. Reliab., 2015

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.
IEEE J. Solid State Circuits, 2015

Emerging resistive memories for low power embedded applications and neuromorphic systems.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Stress management strategy to limit die curvature during silicon interposer integration.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
OxRAM-based non volatile flip-flop in 28nm FDSOI.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014


Joint impact of random variations and RTN on dynamic writeability in 28nm bulk and FDSOI SRAM.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI.
Proceedings of the 44th European Solid State Device Research Conference, 2014

Resistive memories: Which applications?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Cell transformations and physical design techniques for 3D monolithic integrated circuits.
ACM J. Emerg. Technol. Comput. Syst., 2013

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

CMOS SRAM scaling limits under optimum stability constraints.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Back-end 3D integration of HfO2-based RRAMs for low-voltage advanced IC digital design.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

A novel HfO2-GeS2-Ag based conductive bridge RAM for reconfigurable logic applications.
Proceedings of the European Solid-State Device Research Conference, 2013


Thermo-mechanical study of a 2.5D passive silicon interposer technology: Experimental, numerical and In-Situ stress sensors developments.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below.
J. Low Power Electron., 2012

Design challenges for nano-scale devices.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Performance analysis of 3-D monolithic integrated circuits.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2007
Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005
Ultra low voltage design considerations of SOI SRAM memory cells.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Modeling subthreshold SOI logic for static timing analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2004

2003
An SOI 4 transistors self-refresh ultra-low-voltage memory cell.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001
Turning Multi-applications Smart Cards Services Available from Anywhere at Anytime: A SOAP / MOM Approach in the Context of Java Cards.
Proceedings of the Smart Card Programming and Security, 2001


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