Weidong Cao

Orcid: 0000-0001-7539-8250

Affiliations:
  • George Washington University, Department of Electrical and Computer Engineering,
  • Washington University in St. Louis, Department of Electrical and Systems Engineering, St. Louis, MO, USA (PhD 2021)


According to our database1, Weidong Cao authored at least 26 papers between 2015 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

On csauthors.net:

Bibliography

2025
RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization With Knowledge-Infused Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2025

A Hybrid-Domain Floating-Point Compute-in-Memory Architecture for Efficient Acceleration of High-Precision Deep Neural Networks.
CoRR, February, 2025

AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies.
Proceedings of the Thirteenth International Conference on Learning Representations, 2025

2024
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework.
ACM Trans. Design Autom. Electr. Syst., 2024

Addition is Most You Need: Efficient Floating-Point SRAM Compute-in-Memory by Harnessing Mantissa Addition.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
A/D Alleviator: Reducing Analog-to-Digital Conversions in Compute-In-Memory with Augmented Analog Accumulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Non-Hermitian Physics-Inspired Voltage-Controlled Oscillators with Resistive Tuning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

LeCA: In-Sensor Learned Compressive Acquisition for Efficient Machine Vision on the Edge.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

CktGNN: Circuit Graph Neural Network for Electronic Design Automation.
Proceedings of the Eleventh International Conference on Learning Representations, 2023

PDNSig: Identifying Multi-Tenant Cloud FPGAs with Power Distribution Network-Based Signatures.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

RoSE: Robust Analog Circuit Parameter Optimization with Sampling-Efficient Reinforcement Learning.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals.
IEEE Trans. Computers, 2022

Demonstration of fully integrated parity-time-symmetric electronics.
CoRR, 2022

Domain Knowledge-Based Automated Analog Circuit Design with Deep Reinforcement Learning.
CoRR, 2022

HOGEye: Neural Approximation of HOG Feature Extraction in RRAM-Based 3D-Stacked Image Sensors.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

PowerTouch: A Security Objective-Guided Automation Framework for Generating Wired Ghost Touch Attacks on Touchscreens.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Domain knowledge-infused deep learning for automated analog/radio-frequency circuit parameter optimization.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Evaluating Neural Network-Inspired Analog-to-Digital Conversion With Low-Precision RRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020
NeuADC: Neural Network-Inspired Synthesizable Analog-to-Digital Conversion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
Neural Network-Inspired Analog-to-Digital Conversion to Achieve Super-Resolution with Low-Precision RRAM Devices.
Proceedings of the International Conference on Computer-Aided Design, 2019

NeuADC: Neural Network-Inspired RRAM-Based Synthesizable Analog-to-Digital Conversion with Reconfigurable Quantization Support.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.
Microelectron. J., 2018

2016
A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2015
A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015


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