Bo Yuan

Orcid: 0000-0002-3978-2930

Affiliations:
  • Rutgers University, NJ, USA
  • City University of New York, City College, Department of Electrical Engineering, NY, USA (former)
  • University of Minnesota Twin Cities, Department of Electrical and Computer Engineering, MN, USA (PhD 2015)
  • Nanjing University, Institute of VLSI Design, China (former)


According to our database1, Bo Yuan authored at least 138 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2024
When Large Language Models Meet Vector Databases: A Survey.
CoRR, 2024

ELRT: Efficient Low-Rank Training for Compact Convolutional Neural Networks.
CoRR, 2024

MOPED: Efficient Motion Planning Engine with Flexible Dimension Support.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
Algorithm and hardware co-design co-optimization framework for LSTM accelerator using quantized fully decomposed tensor train.
Internet Things, July, 2023

In-Sensor Radio Frequency Computing for Energy-Efficient Intelligent Radar.
CoRR, 2023

GUAP: Graph Universal Attack Through Adversarial Patching.
CoRR, 2023

Learning-based Homography Matrix Optimization for Dual-fisheye Video Stitching.
Proceedings of the 2023 Workshop on Emerging Multimedia Systems, 2023

TDC: Towards Extremely Efficient CNNs on GPUs via Hardware-Aware Tucker Decomposition.
Proceedings of the 28th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, 2023

GraphMP: Graph Neural Network-based Motion Planning with Efficient Graph Search.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Security-Preserving Live 3D Video Surveillance.
Proceedings of the 14th Conference on ACM Multimedia Systems, 2023

DP-DNA: A Digital Pattern-Aware DNA Encoding Scheme to Improve Encoding Density of DNA Storage.
Proceedings of the 31st International Symposium on Modeling, 2023

ETTE: Efficient Tensor-Train-based Computing Engine for Deep Neural Networks.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

DynGMP: Graph Neural Network-Based Motion Planning in Unpredictable Dynamic Environments.
IROS, 2023

COMCAT: Towards Efficient Compression and Customization of Attention-Based Vision Models.
Proceedings of the International Conference on Machine Learning, 2023

Stealthy Backdoor Attack on RF Signal Classification.
Proceedings of the 32nd International Conference on Computer Communications and Networks, 2023

Invited Paper: In-Sensor Radio Frequency Computing for Energy-Efficient Intelligent Radar.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Systolic Array Placement on FPGAs.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

DSPIMM: A Fully Digital SParse In-Memory Matrix Vector Multiplier for Communication Applications.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Accelerable Lottery Tickets with the Mixed-Precision Quantization.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

GOHSP: A Unified Framework of Graph and Optimization-Based Heterogeneous Structured Pruning for Vision Transformer.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

HALOC: Hardware-Aware Automatic Low-Rank Compression for Compact Neural Networks.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

CSTAR: Towards Compact and Structured Deep Neural Networks with Adversarial Robustness.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022
Algorithm and Hardware Co-Design of Energy-Efficient LSTM Networks for Video Recognition With Hierarchical Tucker Tensor Decomposition.
IEEE Trans. Computers, 2022

Algorithm and Hardware Co-Design of Energy-Efficient LSTM Networks for Video Recognition with Hierarchical Tucker Tensor Decomposition.
CoRR, 2022

Audio-domain position-independent backdoor attack via unnoticeable triggers.
Proceedings of the ACM MobiCom '22: The 28th Annual International Conference on Mobile Computing and Networking, Sydney, NSW, Australia, October 17, 2022

Visual privacy protection in mobile image recognition using protective perturbation.
Proceedings of the MMSys '22: 13th ACM Multimedia Systems Conference, Athlone, Ireland, June 14, 2022

Towards Yield Improvement for AI Accelerators: Analysis and Exploration.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Global Placement Exploiting Soft 2D Regularity.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

Robot Motion Planning as Video Prediction: A Spatio-Temporal Neural Network-based Motion Planner.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022

Deep Learning Toolkit-Accelerated Analytical Co-Optimization of CNN Hardware and Dataflow.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Hardware Architecture of Graph Neural Network-Enabled Motion Planner (Invited Paper).
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Invisible and Efficient Backdoor Attacks for Compressed Deep Neural Networks.
Proceedings of the IEEE International Conference on Acoustics, 2022

IMG-SMP: Algorithm and Hardware Co-Design for Real-time Energy-efficient Neural Motion Planning.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

RIBAC: Towards Robust and Imperceptible Backdoor Attack against Compact DNN.
Proceedings of the Computer Vision - ECCV 2022, 2022

HODEC: Towards Efficient High-Order DEcomposed Convolutional Neural Networks.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

VLSI Hardware Architecture of Neural A* Path Planner.
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022

BATUDE: Budget-Aware Neural Network Compression Based on Tucker Decomposition.
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021
Real-time, Robust and Adaptive Universal Adversarial Attacks Against Speaker Recognition Systems.
J. Signal Process. Syst., 2021

PermCNN: Energy-Efficient Convolutional Neural Network Hardware Architecture With Permuted Diagonal Structure.
IEEE Trans. Computers, 2021

Noise Injection-based Regularization for Point Cloud Processing.
CoRR, 2021

CHIP: CHannel Independence-based Pruning for Compact Neural Networks.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

Fake Gradient: A Security and Privacy Protection Framework for DNN-based Image Classification.
Proceedings of the MM '21: ACM Multimedia Conference, Virtual Event, China, October 20, 2021

GoSPA: An Energy-efficient High-performance Globally Optimized SParse Convolutional Neural Network Accelerator.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Graph Universal Adversarial Attacks: A Few Bad Actors Ruin Graph Learning Models.
Proceedings of the Thirtieth International Joint Conference on Artificial Intelligence, 2021

EFM: Elastic Flash Management to Enhance Performance of Hybrid Flash Memory.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Algorithm and Hardware Co-design for Deep Learning-powered Channel Decoder: A Case Study.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

An Efficient Video Prediction Recurrent Network using Focal Loss and Decomposed Tensor Train for Imbalance Dataset.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Towards Efficient Tensor Decomposition-Based DNN Model Compression With Optimization Framework.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

Towards Extremely Compact RNNs for Video Recognition With Fully Decomposed Hierarchical Tucker Structure.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

Robust Detection of Machine-induced Audio Attacks in Intelligent Audio Systems with Microphone Array.
Proceedings of the CCS '21: 2021 ACM SIGSAC Conference on Computer and Communications Security, Virtual Event, Republic of Korea, November 15, 2021

An Efficient Real-Time Object Detection Framework on Resource-Constricted Hardware Devices via Software and Hardware Co-design.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

VLSI Hardware Architecture of Stochastic Low-rank Tensor Decomposition.
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

Doubly Residual Neural Decoder: Towards Low-Complexity High-Performance Channel Decoding.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

Enabling Fast and Universal Audio Adversarial Attack Using Generative Model.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020
Stochastic Belief Propagation Polar Decoding With Efficient Re-Randomization.
IEEE Trans. Veh. Technol., 2020

Compressing Recurrent Neural Networks Using Hierarchical Tucker Tensor Decomposition.
CoRR, 2020

Practical Adversarial Attacks Against Speaker Recognition Systems.
Proceedings of the HotMobile '20: The 21st International Workshop on Mobile Computing Systems and Applications, 2020

VVSec: Securing Volumetric Video Streaming via Benign Use of Adversarial Perturbation.
Proceedings of the MM '20: The 28th ACM International Conference on Multimedia, 2020

How Much Does Regularity Help FPGA Placement?
Proceedings of the International Conference on Field-Programmable Technology, 2020

Real-Time, Universal, and Robust Adversarial Attacks Against Speaker Recognition Systems.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

Reduced-Complexity Singular Value Decomposition For Tucker Decomposition: Algorithm And Hardware.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

AdvPulse: Universal, Synchronization-free, and Targeted Audio Adversarial Attacks via Subsecond Perturbations.
Proceedings of the CCS '20: 2020 ACM SIGSAC Conference on Computer and Communications Security, 2020

Low-complexity Neural Network-based MIMO Detector using Permuted Diagonal Matrix.
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020

VLSI Hardware Architecture for Gaussian Process.
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020

CAG: A Real-Time Low-Cost Enhanced-Robustness High-Transferability Content-Aware Adversarial Attack Generator.
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020

Embedding Compression with Isotropic Iterative Quantization.
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020

2019
Reduced-Complexity Deep Neural Networks Design Using Multi-Level Compression.
IEEE Trans. Sustain. Comput., 2019

HEIF: Highly Efficient Stochastic Computing-Based Inference Framework for Deep Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Neural Network Classifiers Using a Hardware-Based Approximate Activation Function with a Hybrid Stochastic Multiplier.
ACM J. Emerg. Technol. Comput. Syst., 2019

Normalization and dropout for stochastic computing-based deep convolutional neural networks.
Integr., 2019

CircConv: A Structured Convolution with Low Complexity.
CoRR, 2019

Structured Neural Network with Low Complexity for MIMO Detection.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019

Hardware Acceleration of Persistent Homology Computation.
Proceedings of the Large-Scale Annotation of Biomedical Data and Expert Label Synthesis and Hardware Aware Learning for Medical Imaging and Computer Assisted Intervention, 2019

TIE: energy-efficient tensor train-based inference engine for deep neural network.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

HAML-SSD: A Hardware Accelerated Hotness-Aware Machine Learning based SSD Management.
Proceedings of the International Conference on Computer-Aided Design, 2019

High-performance Hardware Architecture for Tensor Singular Value Decomposition: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

Compressing Deep Neural Networks Using Toeplitz Matrix: Algorithm Design and Fpga Implementation.
Proceedings of the IEEE International Conference on Acoustics, 2019

Reduced-complexity Deep Neural Network-aided Channel Code Decoder: A Case Study for BCH Decoder.
Proceedings of the IEEE International Conference on Acoustics, 2019

Universal Approximation Property and Equivalence of Stochastic Computing-Based Neural Networks and Binary Neural Networks.
Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019

CircConv: A Structured Convolution with Low Complexity.
Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019

2018
Introduction to the Special Issue on Signal Processing Systems.
J. Signal Process. Syst., 2018

SGAD: Soft-Guided Adaptively-Dropped Neural Network.
CoRR, 2018

PermDNN: Efficient Compressed DNN Architecture with Permuted Diagonal Matrices.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Towards Theoretical Cost Limit of Stochastic Number Generators for Stochastic Computing.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks Using Stochastic Computing.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Quantized neural networks with new stochastic multipliers.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAs.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Large-scale short-term urban taxi demand forecasting using deep learning.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Area-efficient K-Nearest Neighbor Design using Stochastic Computing.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

Efficient Reconfigurable Hardware Core for Convolutional Neural Networks.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

Towards Ultra-High Performance and Energy Efficiency of Deep Learning Systems: An Algorithm-Hardware Co-Optimization Framework.
Proceedings of the Thirty-Second AAAI Conference on Artificial Intelligence, 2018

2017
LLR-Based Successive-Cancellation List Decoder for Polar Codes With Multibit Decision.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Fully-Parallel Area-Efficient Deep Neural Network Design Using Stochastic Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Reliable PUF-Based Local Authentication With Self-Correction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

VLSI Architectures for the Restricted Boltzmann Machine.
ACM J. Emerg. Technol. Comput. Syst., 2017

CirCNN: Accelerating and Compressing Deep Neural Networks Using Block-CirculantWeight Matrices.
CoRR, 2017

Theoretical Properties for Neural Networks with Weight Matrices of Low Displacement Rank.
CoRR, 2017

Efficient fast convolution architecture based on stochastic computing.
Proceedings of the 9th International Conference on Wireless Communications and Signal Processing, 2017

Memristor crossbar-based ultra-efficient next-generation baseband processors.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

CirCNN: accelerating and compressing deep neural networks using block-circulant weight matrices.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Theoretical Properties for Neural Networks with Weight Matrices of Low Displacement Rank.
Proceedings of the 34th International Conference on Machine Learning, 2017

Neural Network Classifiers Using Stochastic Computing with a Hardware-Oriented Approximate Activation Function.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Energy-efficient, high-performance, highly-compressed deep neural network design using block-circulant matrices.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Softmax Regression Design for Stochastic Computing Based Deep Convolutional Neural Networks.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Structural design optimization for deep convolutional neural networks using stochastic computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

SC-DCNN: Highly-Scalable Deep Convolutional Neural Network using Stochastic Computing.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

Towards acceleration of deep convolutional neural networks using stochastic computing.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Area-Efficient Scaling-Free DFT/FFT Design Using Stochastic Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

LLR-based Successive-Cancellation List Decoder for Polar Codes with Multi-bit Decision.
CoRR, 2016

Design of high-speed low-power polar BP decoder using emerging technologies.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A low-computation-complexity, energy-efficient, and high-performance linear program solver using memristor crossbars.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Synthesis of Probability Theory Based on Molecular Computation.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

High-Accuracy FIR Filter Design Using Stochastic Computing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Memristor-Based Discrete Fourier Transform for Improving Performance and Energy Efficiency.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Area-efficient scaling-free DFT/FFT design using stochastic computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Belief propagation decoding of polar codes using stochastic computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Designing reconfigurable large-scale deep learning systems using stochastic computing.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

DSCNN: Hardware-oriented optimization for Stochastic Computing based Deep Convolutional Neural Networks.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Design space exploration for hardware-efficient stochastic computing: A case study on discrete cosine transformation.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Area-Efficient Error-Resilient Discrete Fourier Transformation Design using Stochastic Computing.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Low-Latency Successive-Cancellation List Decoders for Polar Codes With Multibit Decision.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Successive cancellation decoding of polar codes using stochastic computing.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Reduced-latency LLR-based SC List Decoder for Polar Codes.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Early Stopping Criteria for Energy-Efficient Low-Latency Belief-Propagation Polar Code Decoders.
IEEE Trans. Signal Process., 2014

Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Low-Latency Successive-Cancellation List Decoders for Polar Codes with Multi-bit Decision.
CoRR, 2014

Architectures for polar BP decoders using folding.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Efficient adaptive list successive cancellation decoder for polar codes.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

Algorithm and architecture for hybrid decoding of polar codes.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

Successive cancellation list polar decoder using log-likelihood ratios.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
Architecture optimizations for BP polar decoders.
Proceedings of the IEEE International Conference on Acoustics, 2013

2012
Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Reduced-latency SC polar decoder architectures.
Proceedings of IEEE International Conference on Communications, 2012

2011
Low-Latency SC Decoder Architectures for Polar Codes
CoRR, 2011

2009
Area-efficient reed-solomon decoder design for optical communications.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Area-efficient Reed-Solomon Decoder Design for 10-100 Gb/s Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009


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