Kyungwook Chang

Orcid: 0000-0002-8513-9890

According to our database¹, Kyungwook Chang authored at least 27 papers between 2009 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2024

Pin-3D: Effective Physical Design Methodology for Multidie Co-Optimization in Monolithic 3-D ICs.

[BibT_eX]

[DOI]

Sai Pentapati

Kyungwook Chang

Sung Kyu Lim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

2023

Parameter Optimization of VLSI Placement Through Deep Reinforcement Learning.

[BibT_eX]

[DOI]

Anthony Agnesina

Kyungwook Chang

Sung Kyu Lim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

2022

Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors.

[BibT_eX]

[DOI]

Lingjun Zhu

Lennart Bamberg

Sai Surya Kiran Pentapati

IEEE Trans. Very Large Scale Integr. Syst., 2021

Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2021

2020

Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs.

[BibT_eX]

[DOI]

Bon Woong Ku

Kyungwook Chang

Sung Kyu Lim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs.

[BibT_eX]

[DOI]

Sai Surya Kiran Pentapati

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

VLSI Placement Parameter Optimization using Deep Reinforcement Learning.

[BibT_eX]

[DOI]

Anthony Agnesina

Kyungwook Chang

Sung Kyu Lim

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Sung Kyu Lim

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Power, Performance, and Area Benefit of Monolithic 3D ICs for On-Chip Deep Neural Networks Targeting Speech Recognition.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2018

Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs.

[BibT_eX]

[DOI]

Bon Woong Ku

Kyungwook Chang

Sung Kyu Lim

Proceedings of the 2018 International Symposium on Physical Design, 2018

Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

2017

Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Frequency and time domain analysis of power delivery network for monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper).

[BibT_eX]

[DOI]

Kyungwook Chang

Abhishek Koneru

Krishnendu Chakrabarty

Sung Kyu Lim

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

Monolithic 3D IC design: Power, performance, and area impact at 7nm.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Match-making for monolithic 3D IC: finding the right technology node.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Power benefit study of monolithic 3D IC at the 7nm technology node.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2010

Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution.

[BibT_eX]

[DOI]

Ganghee Lee

Kyungwook Chang

Kiyoung Choi

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Memory-Centric Communication Architecture for Reconfigurable Computing.

[BibT_eX]

[DOI]

Kyungwook Chang

Kiyoung Choi

Proceedings of the Reconfigurable Computing: Architectures, 2010

2009

Coarse-grained reconfigurable architecture for multiple application domains: a case study.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009

Kyungwook Chang

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