Frank Lee

Affiliations:

Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan

According to our database¹, Frank Lee authored at least 15 papers between 2012 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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On csauthors.net:

Bibliography

2025

TSMC in the Silicon Photonics Era - an Electrical Perspective.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2025

2024

An On-Chip Current-Sink-Free Adaptive-Timing Power Impedance Measurement (PIM) Unit for 3D-IC in 5nm FinFET Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2024

Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests.

[BibT_eX]

[DOI]

Bharath Shankaranarayanan

Doo Kim

Manish Arora

Proceedings of the IEEE International Test Conference, 2024

Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area Impact.

[BibT_eX]

[DOI]

Sandeep Kumar Goel

Ankita Patidar

Frank Lee

Proceedings of the IEEE European Test Symposium, 2024

2021

Physical Design for 3D Chiplets and System Integration.

[BibT_eX]

[DOI]

Frank J. C. Lee

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Energy Efficient Design Through Design and Technology Co-Optimization Near the Finish Line of CMOS Scaling.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing.

[BibT_eX]

[DOI]

Kenny Cheng-Hsiang Hsieh

IEEE J. Solid State Circuits, 2020

2019

A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing.

[BibT_eX]

[DOI]

Kenny Cheng-Hsiang Hsieh

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2015

Efficient observation-point insertion for diagnosability enhancement in digital circuits.

[BibT_eX]

[DOI]

Zipeng Li

Sandeep Kumar Goel

Frank Lee

Krishnendu Chakrabarty

Proceedings of the 2015 IEEE International Test Conference, 2015

2014

Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs.

[BibT_eX]

[DOI]

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

2013

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

3DIC from concept to reality.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Frank Lee

Timeline

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