Hongbin Sun

According to our database1, Hongbin Sun authored at least 74 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
Algorithm and VLSI Architecture Co-Design on Efficient Semi-Global Stereo Matching.
IEEE Trans. Circuits Syst. Video Technol., 2020

A 4K × 2K@60fps Multifunctional Video Display Processor for High Perceptual Image Quality.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Spatiotemporal neural networks for action recognition based on joint loss.
Neural Comput. Appl., 2020

ADCPNet: Adaptive Disparity Candidates Prediction Network for Efficient Real-Time Stereo Matching.
CoRR, 2020

Designing Efficient Shortcut Architecture for Improving the Accuracy of Fully Quantized Neural Networks Accelerator.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Exploiting Variable Precision Computation Array for Scalable Neural Network Accelerators.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
Efficient Compression-Based Line Buffer Design for Image/Video Processing Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Learning Composite Latent Structures for 3D Human Action Representation and Recognition.
IEEE Trans. Multim., 2019

NIPM-sWMF: Toward Efficient FPGA Design for High-Definition Large-Disparity Stereo Matching.
IEEE Trans. Circuits Syst. Video Technol., 2019

Architectural Exploration to Address the Reliability Challenges for ReRAM-Based Buffer in SSD.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Learnable Tree Filter for Structure-preserving Feature Transform.
Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019

Scene-Guided Region Proposal Re-ranking Method for On-road Vehicle Candidate Generation.
Proceedings of the 2019 IEEE Intelligent Vehicles Symposium, 2019

A Benchmark Dataset and Multi-Scale Attention Network for Semantic Traffic Light Detection.
Proceedings of the 2019 IEEE Intelligent Transportation Systems Conference, 2019

A Hardware-Efficient Post-Processing Algorithm for Motion Compensated Frame Rate Up-Conversion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

REcache: Efficient Sustainable Energy Management Circuits and Policies for Computing Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Exploring Hardware Friendly Bottleneck Architecture in CNN for Embedded Computing Systems.
Proceedings of the 2019 IEEE International Conference on Image Processing, 2019

TACNet: Transition-Aware Context Network for Spatio-Temporal Action Detection.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019

Efficient Photometric Alignment for Around View Monitor System.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Exploring Customizable Heterogeneous Power Distribution and Management for Datacenter.
IEEE Trans. Parallel Distributed Syst., 2018

Worst Case Driven Display Frame Compression for Energy-Efficient Ultra-HD Display Processing.
IEEE Trans. Multim., 2018

VLSI Architecture Exploration of Guided Image Filtering for 1080P@60Hz Video Processing.
IEEE Trans. Circuits Syst. Video Technol., 2018

Efficient Rectangle Fitting of Sparse Laser Data for Robust On-Road Obiect Detection.
Proceedings of the 2018 IEEE Intelligent Vehicles Symposium, 2018

Leveraging Spatio-Temporal Evidence and Independent Vision Channel to Improve Multi-Sensor Fusion for Vehicle Environmental Perception.
Proceedings of the 2018 IEEE Intelligent Vehicles Symposium, 2018

Exploring the Potential of Using Semantic Context and Common Sense in On-Road Vehicle Detection.
Proceedings of the 2018 IEEE Intelligent Vehicles Symposium, 2018

Human-Like Maneuver Decision Using LSTM-CRF Model for On-Road Self-Driving.
Proceedings of the 21st International Conference on Intelligent Transportation Systems, 2018

Spatial-Temporal Neural Networks for Action Recognition.
Proceedings of the Artificial Intelligence Applications and Innovations, 2018

Exploring Resource-Aware Deep Neural Network Accelerator and Architecture Design.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

A 4K×2K@60fps Multi-format Multi-function Display Processor for High Perceptual Quality.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Managing Battery Aging for High Energy Availability in Green Datacenters.
IEEE Trans. Parallel Distributed Syst., 2017

Toward an Efficient Multiview Display Processing Architecture for 3DTV.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Improving 3D DRAM Fault Tolerance Through Weak Cell Aware Error Correction.
IEEE Trans. Computers, 2017

sWMF: Separable weighted median filter for efficient large-disparity stereo matching.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Zynq-based full HD around view monitor system for intelligent vehicle.
Proceedings of the 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2017

2016
Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device.
IEEE Trans. Very Large Scale Integr. Syst., 2016

RE-UPS: an adaptive distributed energy storage system for dynamically managing solar energy in green datacenters.
J. Supercomput., 2016

Integrated Longitudinal and Lateral Control for Kuafu-II Autonomous Vehicle.
IEEE Trans. Intell. Transp. Syst., 2016

On-Road Vehicle Detection and Tracking Using MMW Radar and Monovision Fusion.
IEEE Trans. Intell. Transp. Syst., 2016

Algorithm and VLSI Architecture of Edge-Directed Image Upscaling for 4k Display System.
IEEE Trans. Circuits Syst. Video Technol., 2016

A 128 Kb HfO<sub>2</sub> ReRAM with Novel Double-Reference and Dynamic-Tracking scheme for write yield improvement.
IEICE Electron. Express, 2016

On the Use of DRAM with Unrepaired Weak Cells in Computing Systems.
Proceedings of the Second International Symposium on Memory Systems, 2016

Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloud.
Proceedings of the Second International Symposium on Memory Systems, 2016

Exploring the use of volatile STT-RAM for energy efficient video processing.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Towards an Adaptive Multi-Power-Source Datacenter.
Proceedings of the 2016 International Conference on Supercomputing, 2016

2015
Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Leveraging Heterogeneous Power for Improving Datacenter Efficiency and Resiliency.
IEEE Comput. Archit. Lett., 2015

VLSI Design of Edge-Preserving Coding Artifacts Reduction for Display Processing.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Exploiting bit-depth scaling for quality-scalable energy efficient display processing.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

HEB: deploying and managing hybrid energy buffers for improving datacenter efficiency and economy.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

BAAT: Towards Dynamically Managing Battery Aging in Green Datacenters.
Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015

Logic-DRAM co-design to efficiently repair stacked DRAM with unused spares.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

An experimental study on the potential use of ReRAM as SSD buffer.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Improving min-sum LDPC decoding throughput by exploiting intra-cell bit error characteristic in MLC NAND flash memory.
Proceedings of the IEEE 30th Symposium on Mass Storage Systems and Technologies, 2014

Design and implementation of driving control system for autonomous vehicle.
Proceedings of the 17th International IEEE Conference on Intelligent Transportation Systems, 2014

Bionic vision inspired on-road obstacle detection and tracking using radar and visual information.
Proceedings of the 17th International IEEE Conference on Intelligent Transportation Systems, 2014

Leveraging distributed UPS energy for managing solar energy powered data centers.
Proceedings of the International Green Computing Conference, 2014

2013
Using Planar Embedded DRAM in Memory Intensive Signal Processing Circuits: Case Studies on LDPC Decoding and Motion Estimation.
J. Signal Process. Syst., 2013

Exploring the Use of Emerging Nonvolatile Memory Technologies in Future FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Scheduling Algorithms for Handling Updates in Shingled Magnetic Recording.
Proceedings of the IEEE Eighth International Conference on Networking, 2013

LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives.
Proceedings of the 11th USENIX conference on File and Storage Technologies, 2013

VLSI design of fuzzy-decision bit-flipping QC-LDPC decoder.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Reducing latency overhead caused by using LDPC codes in NAND flash memory.
EURASIP J. Adv. Signal Process., 2012

Design and implementation of a video display processing SoC for full HD LCD TV.
Proceedings of the International SoC Design Conference, 2012

An edge-based adaptive image interpolation and its VLSI architecture.
Proceedings of the Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2012

2011
Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM).
IEEE Trans. Very Large Scale Integr. Syst., 2011

Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology.
Microprocess. Microsystems, 2011

Design techniques to improve the device write margin for MRAM-based cache memory.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

A high performance and low cost video processing SoC for digital HDTV systems.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2009
Leveraging Access Locality for the Efficient Use of Multibit Error-Correcting Codes in L2 Cache.
IEEE Trans. Computers, 2009

3D DRAM Design and Application to 3D Multicore Systems.
IEEE Des. Test Comput., 2009

Architecture design exploration of three-dimensional (3D) integrated DRAM.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Realization of L2 Cache Defect Tolerance Using Multi-bit ECC.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008


  Loading...