Shengwen Liang

Orcid: 0000-0001-8407-2594

According to our database1, Shengwen Liang authored at least 42 papers between 2019 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
QiMeng: Fully Automated Hardware and Software Design for Processor Chip.
CoRR, June, 2025

Large Processor Chip Model.
CoRR, June, 2025

CodeV-R1: Reasoning-Enhanced Verilog Generation.
CoRR, May, 2025

APoX-M: Accelerate deep point cloud analysis via adaptive graph construction.
Integr., 2025

HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion.
Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

Frontier-guided Graph Reordering.
Proceedings of the 30th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, 2025

Graphitron: A Domain Specific Language for FPGA-Based Graph Processing Accelerator Generation.
Proceedings of the 26th ACM SIGPLAN/SIGBED International Conference on Languages, 2025

XHarvest: Rethinking High-Performance and Cost-Efficient SSD Architecture with CXL-Driven Harvesting.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

Taijigraph: an Out-Of-Core Graph Processing System Enhanced with Computational Storage.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2025

FrontOrder: Frontier-Guided Graph Reordering.
Proceedings of the 41st IEEE International Conference on Data Engineering, 2025

NeuVSA: A Unified and Efficient Accelerator for Neural Vector Search.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

InstAttention: In-Storage Attention Offloading for Cost-Effective Long-Context LLM Inference.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2024

DRIM-ANN: An Approximate Nearest Neighbor Search Engine based on Commercial DRAM-PIMs.
CoRR, 2024

InstInfer: In-Storage Attention Offloading for Cost-Effective Long-Context LLM Inference.
CoRR, 2024

Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation.
CoRR, 2024

Cambricon-LLM: A Chiplet-Based Hybrid Architecture for On-Device Inference of 70B LLM.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Flagger: Cooperative Acceleration for Large-Scale Cross-Silo Federated Learning Aggregation.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

AGC: A Unified Architecture for Accelerating K-Nearest Neighbor Graph Construction in Vector Search.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

HyQA: Hybrid Near-Data Processing Platform for Embedding Based Question Answering System.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

GPACE: An Energy-Efficient PQ-Based GCN Accelerator with Redundancy Reduction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

SmartATPG: Learning-based Automatic Test Pattern Generation with Graph Convolutional Network and Reinforcement Learning.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Chiplever: Towards Effortless Extension of Chiplet-based System for FHE.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
ChipGPT: How far are we from natural language hardware design.
CoRR, 2023

PANG: A Pattern-Aware GCN Accelerator for Universal Graphs.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Intelligent Automatic Test Pattern Generation for Digital Circuits Based on Reinforcement Learning.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022
Cognitive SSD+: a deep learning engine for energy-efficient unstructured data retrieval.
CCF Trans. High Perform. Comput., 2022

VStore: in-storage graph based vector search accelerator.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks.
IEEE Trans. Computers, 2021

GLIST: Towards In-Storage Graph Learning.
Proceedings of the 2021 USENIX Annual Technical Conference, 2021

GCiM: A Near-Data Processing Accelerator for Graph Construction.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021


2020
DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval.
Proceedings of the 2019 USENIX Annual Technical Conference, 2019

InS-DLA: An In-SSD Deep Learning Accelerator for Near-Data Processing.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019


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