A Reference-Less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed.

[BibT_eX]

[DOI]

Xiaoteng Zhao

Yuhao Zhang

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

19.11 A 13GHz Charge-Pump PLL Achieving 15.8fsrms Integrated Jitter and -98.5dBc Reference Spur.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

24.2 A 14b 1GS/s Single-Channel Pipelined ADC with A Parallel-Operation SAR Sub-Quantizer and A Dynamic-Deadzone Ring Amplifier.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

An 18-Bit 183.9dB-FoMS, DR MES/Calibration-Free Scalable Zoom ADC Using Fully Passive Coarse Modulator and Gain-Linearity-Enhanced FIA with Sub-1ppm-THD at Full Scale Input in 65-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

A 32GS/s 8b 16× Time-Interleaved Hybrid ADC with Self-Detection Offset Calibration, DLL-Based TLSB PVT Variation Calibration and VTC Gain Self-Tracking.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

A 100Gb/s Transmitter with Digital Pre-Distortion and MUX-Merged Voltage-Mode Driver Achieving 3-Times INLPP Improvement in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

A 0.7-V 26.2-28.5 GHz Dual-Loop Double-Sampling PLL with Floating Capacitor OTA Based Gm-CP Achieving a 45.4-fsRMS Jitter.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, November, 2024

A 182.9-dB FoM 108.2-dB SFDR Power/Bandwidth Configurable Fully Dynamic Switched-Capacitor Zoom ADC With Interstage Leakage Shaping.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2024

A Wideband Input Buffer Based on Cascade Complementary Source Follower.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., May, 2024

A 3.96-4.84-GHz Dual-Path Charge Pump PLL Achieving 89.7-fsrms Integrated Jitter and -250.8-dB FOMPLL.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

A High Accuracy and Bandwidth Digital Background Calibration Technique for Timing Skew in TI-ADCs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

A -64.3 dB THD, 26 nV/√ Hz Bio-Potential Readout Analog-Front-End Amplifier With a Gm-C Integrator-Implanted DC Servo Loop, and a Bulk-Driven Ripple Reduction Loop.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

A wideband low power RF Receiver Front-End for Internet-of-Things applications.

[BibT_eX]

[DOI]

Microelectron. J., February, 2024

A 8.1-nW, 4.22-kHz, -40-85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications.

[BibT_eX]

[DOI]

Microelectron. J., February, 2024

High Power-Efficiency Readout Circuit for MEMS Capacitive Accelerometer.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

A 14b 180MS/s Pipeline-SAR ADC With Adaptive-Region-Selection Technique and Gain Error Calibration.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

LUT-Assisted Particle Swarm Optimization-Based Bit-Weight Calibration for SAR ADCs.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2024

A Background Timing Skew Calibration for Time-Interleaved ADCs Based on Frequency Fitness Genetic Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2024

A chopper instrumentation amplifier with discrete-time compensation based on current generation unit to eliminate electrode DC offset.

[BibT_eX]

[DOI]

Microelectron. J., 2024

A low-noise, 0.05-17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators.

[BibT_eX]

[DOI]

Microelectron. J., 2024

An instrumentation amplifier with series switch pseudo resistor DC-servo loop realizing 0.16-Hz high-pass corner.

[BibT_eX]

[DOI]

Microelectron. J., 2024

An auto-zeroing chopper-stabilized capacitively coupled instrumentation amplifier with 25-Vpp common-mode interference tolerance.

[BibT_eX]

[DOI]

Microelectron. J., 2024

Power-efficient 12-bit 800 MS/s voltage-time hybrid domain ADC with split TDC in 28 nm CMOS.

[BibT_eX]

[DOI]

Microelectron. J., 2024

A high constancy and noise suppression voltage shift generator in SEIR-based BIST circuit for ADC linearity test.

[BibT_eX]

[DOI]

Microelectron. J., 2024

A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique.

[BibT_eX]

[DOI]

Microelectron. J., 2024

A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry.

[BibT_eX]

[DOI]

Microelectron. J., 2024

A 2nd-order noise-shaping SAR-assisted pipeline ADC with order-boosted gain-error-shaping.

[BibT_eX]

[DOI]

Microelectron. J., 2024

A 10-GS/s 8-bit 2× time interleaved hybrid ADC with λ/4 reference T-Line sharing technique.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2024

A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2024

A wide load-range OTA using a digitally assisted compensating technique.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2024

5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Low-Cost Linearity Testing of High-Resolution ADCs Using Segmentation Modeling and Partial Polynomial Fitting.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm2 Area.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A 0.9-V Supply Up to 21.5-dB Boost Gain Analog Front-End with T-coilloaded CTLE and VGA in 28-nm CMOS for 112-Gb/s PAM-4 Medium-Reach Receivers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2024

A 0.64mm2Sensor Size, 32.5μg/√Hz Noise Floor, High Efficiency MEMS Capacitive Accelerometer Using High-Voltage Pulse Excitation Technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

A 737nA Always-On MEMS Gyroscope with 5.45ms Start-up Time Using Burst Mode PLL Technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

A 2.4 GHz Ultra-Low-Power Low-Voltage Temperature-Stable Transmitter for Biosensing Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2024

A 0.0006-mm2 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

A 14b Calibration-Free Pipelined SAR ADC Using a Single-Stage Gain Boost FIA.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

A 14.6-ENOB Second-Order Noise-Shaping SAR ADC With kT/C Noise Shifting.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

An Energy-Efficient Look-up Table Framework for Super Resolution on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

A High Precision CV Control Scheme for Low Power AC-DC BUCK Converter Controller.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023

A 44-μW, 91.3-dB SNDR DT Δ Σ Modulator With Second-Order Noise-Shaping SAR Quantizer.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

A 0.26 μVrms instrumentation amplifier based on discrete-time DC servo loop with successive-approximation-compensation technique and Chopper DAC Array.

[BibT_eX]

[DOI]

Microelectron. J., September, 2023

An offset and gain error calibration method in high-precision SAR ADCs.

[BibT_eX]

[DOI]

Microelectron. J., September, 2023

An All-Digital Background Calibration Technique for M-Channel Downsampling Time-Interleaved ADCs Based on Interpolation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

A 63 μg/√Hz Noise Floor and 14 pJ Power Efficiency Open-Loop MEMS Capacitive Accelerometer Using Closed-Loop Hybrid Dynamic Amplifier.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023

An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

A 100- to- 10-kHz 5.4- to- 216- μW Power-Efficient Readout Circuit Employing Closed-Loop Dynamic Amplifier for MEMS Capacitive Accelerometer.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2023

A Single-Channel 70dB-SNDR 100MHz-BW 4th-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A 0.012mm2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

An 83.6dB-SNDR 101.6dB-SFDR 4th-Order Noise-Shaping SAR with 2nd-Order Nonlinearity Error Shaping.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A $142.8-\mu \text{W}$ 98.1dB-SNDR Power/Bandwidth Configurable Fully Dynamic Discrete-Time Zoom ADC with Interstage Leakage Shaping.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A 5GS/s 38.04dB SNDR Single-Channel TDC-Assisted Hybrid ADC with $\lambda/4$ Transmission Line Based Time Quantizer Achieving a PVT Robustness 416.6fs Time Step.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

A 77.8dB-SNDR 25MHz-BW 2nd-order NS Pipelined SAR ADC with 4th-order Gain-Error-Shaping.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Correlated Double Amplifying Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer.

[BibT_eX]

[DOI]

Longjie Zhong

Shubin Liu

Donglai Xu

IEEE Trans. Instrum. Meas., 2022

A 625kHz-BW, 79.3dB-SNDR Second-Order Noise-Shaping SAR ADC Using High-Efficiency Error-Feedback Structure.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 0.018 %/V Line Sensitivity Voltage Reference With -82.46 dB PSRR at 100 Hz for Bio-Potential Signals Readout Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Power-Efficient TVC-Based Fast Auto-Frequency Calibration for PLLs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 10-Bit 2.5-GS/s Two-Step ADC With Selective Time-Domain Quantization in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2022

Capacitance-to-voltage converter employing parallel-series passive charge integrator for low noise power efficient MEMS capacitive sensor.

[BibT_eX]

[DOI]

Microelectron. J., 2022

A configurable nonbinary 7/8-bit 800-400 MS/s SAR ADC in 65 nm CMOS.

[BibT_eX]

[DOI]

Henghui Mao

Dengquan Li

Shubin Liu

Microelectron. J., 2022

Radio frequency analog-to-digital converters: Systems and circuits review.

[BibT_eX]

[DOI]

Microelectron. J., 2022

A loop-unrolled assisted 9b 700 MS/s nonbinary 2b/cycle SAR ADC with time-based offset calibration.

[BibT_eX]

[DOI]

Microelectron. J., 2022

An efficient EEGNet processor design for portable EEG-Based BCIs.

[BibT_eX]

[DOI]

Microelectron. J., 2022

A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

Analysis and Design of a High-Bandwidth Front-End Sampler for Time-Interleaved ADCs.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2022

A Wideband High-linearity Input Buffer Based on Cascade Complementary Source Follower.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021

A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

A statistical offset calibration technique for 1.5-bit/cycle SAR ADCs.

[BibT_eX]

[DOI]

Microelectron. J., 2021

A 2.6 GΩ, 1.4 μVrms current-reuse instrumentation amplifier for wearable electrocardiogram monitoring.

[BibT_eX]

[DOI]

Microelectron. J., 2021

A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020

An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 2nd-Order Noise-Shaping SAR ADC With Lossless Dynamic Amplifier Assisted Integrator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 7b 400 MS/s pipelined SAR ADC in 65 nm CMOS.

[BibT_eX]

[DOI]

Microelectron. J., 2020

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019

A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-µm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 1.2-V 2.41-GHz Three-Stage CMOS OTA With Efficient Frequency Compensation Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018

Low-Power Single-Ended SAR ADC Using Symmetrical DAC Switching for Image Sensors With Passive CDS and PGA Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Energy-Efficient and Area-Saving Asymmetric Capacitor Switching Scheme for SAR ADCs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2018

A 10-KS/s 625-Hz-Bandwidth 60-dB SNDR Noise-Shaping ADC for Bio-potential Signals Detection Application.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

A low-noise programmable gain amplifier with fully balanced differential difference amplifier and class-AB output stage.

[BibT_eX]

[DOI]

Microelectron. J., 2017

Analysis and optimal distribution scheme for SAR-VCO ADCs.

[BibT_eX]

[DOI]

Microelectron. J., 2017

2016

A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching.

[BibT_eX]

[DOI]

Shubin Liu

Yi Shen

Zhangming Zhu

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS.

[BibT_eX]

[DOI]

Yi Shen

Shubin Liu

Zhangming Zhu

Microelectron. J., 2016

An automatic mode low-jitter pulsewidth control loop with broadband operation frequency.

[BibT_eX]

[DOI]

Shubin Liu

Wei Guo

Zhangming Zhu

Microelectron. J., 2016

An asynchronous 12-bit 50 MS/s rail-to-rail Pipeline-SAR ADC in 0.18 μm CMOS.

[BibT_eX]

[DOI]

Wei Guo

Shubin Liu

Zhangming Zhu

Microelectron. J., 2016

2013

A Low Offset Comparator for High Speed Low Power ADC.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2013

A low-jitter pulsewidth control loop with high supply noise rejection.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2013

2012

A CMOS 4.6ppm/°C curvature-compensated bandgap voltage reference.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2012

Shubin Liu

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