Yang Guo

According to our database, Yang Guo authored at least 99 papers between 2003 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2024

A Survey of Design and Optimization for Systolic Array-based DNN Accelerators.

Rui Xu, Sheng Ma, Yang Guo, Dongsheng Li

ACM Comput. Surv., January, 2024

2023

A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization.

Xu He, Yao Wang, Zhiyong Fu, Yipei Wang, Yang Guo

ACM Trans. Design Autom. Electr. Syst., November, 2023

A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits.

Xu He, Yao Wang, Chang Liu, Qiang Wu, Juan Luo, Yang Guo

ACM Trans. Design Autom. Electr. Syst., July, 2023

Design of three-factor secure and efficient authentication and key-sharing protocol for IoT devices.

Zhenyu Wang, Ding Deng, Shen Hou, Yang Guo, Shaoqing Li

Comput. Commun., April, 2023

2022

Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators.

Rui Xu, Sheng Ma, Yaohua Wang, Yang Guo, Dongsheng Li, Yuran Qiao

IEEE Trans. Parallel Distributed Syst., 2022

A Single-Event Transient Radiation Hardened Low-Dropout Regulator for LC Voltage-Controlled Oscillator.

Xi Chen, Qian-cheng Guo, Hengzhou Yuan, Yang Guo

Symmetry, 2022

MT-3000: a heterogeneous multi-zone processor for HPC.

Kai Lu, Yaohua Wang, Yang Guo, Chun Huang, Sheng Liu, Ruibo Wang, Jianbin Fang, Tao Tang, Zhaoyun Chen, Biwei Liu, Zhong Liu, Yuanwu Lei, Haiyan Sun

CCF Trans. High Perform. Comput., 2022

Mentha: Enabling Sparse-Packing Computation on Systolic Arrays.

Minjin Tang, Mei Wen, Yasong Cao, Junzhong Shen, Jianchao Yang, Jiawei Fei, Yang Guo, Sheng Liu

Proceedings of the 51st International Conference on Parallel Processing, 2022

HCRO-LKSM: A Lightweight Key Sharing and Management Protocol Based on HCRO-PUF for IoT Devices.

Zhenyu Wang, Ding Deng, Yang Guo, Shaoqing Li

Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022

Accurate timing prediction at placement stage with look-ahead RC network.

Xu He, Zhiyong Fu, Yao Wang, Chang Liu, Yang Guo

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks.

Rui Xu, Sheng Ma, Yaohua Wang, Xinhai Chen, Yang Guo

ACM Trans. Archit. Code Optim., 2021

Current mirror with charge dissipation transistor for analogue single-event transient mitigation in space application.

Jingtian Liu, Bin Liang, Jianjun Chen, Yaqing Chi, Li Yan, Yang Guo

IET Circuits Devices Syst., 2021

A New Bidirectional Unsupervised Domain Adaptation Segmentation Framework.

Munan Ning, Cheng Bian, Dong Wei, Chenglang Yuan, Yaohua Wang, Yang Guo, Kai Ma, Yefeng Zheng

CoRR, 2021

Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions.

Yaohua Wang, Chen Li, Chang Liu, Sheng Liu, Yuanwu Lei, Jian Zhang, Yang Zhang, Yang Guo

CCF Trans. High Perform. Comput., 2021

A dynamically configurable LFSR-based PUF design against machine learning attacks.

Shen Hou, Ding Deng, Zhenyu Wang, Jiahe Shi, Shaoqing Li, Yang Guo

CCF Trans. High Perform. Comput., 2021

Editorial for the special issue on reliability and power efficiency for HPC.

Jifeng He, Chenggang Wu, Huawei Li, Yang Guo, Tao Li

CCF Trans. High Perform. Comput., 2021

A New Bidirectional Unsupervised Domain Adaptation Segmentation Framework.

Munan Ning, Cheng Bian, Dong Wei, Shuang Yu, Chenglang Yuan, Yaohua Wang, Yang Guo, Kai Ma, Yefeng Zheng

Proceedings of the Information Processing in Medical Imaging, 2021

Improving Inter-kernel Data Reuse With CTA-Page Coordination in GPGPU.

Xuanyi Li, Chen Li, Yang Guo, Rachata Ausavarungnirun

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

HeSA: Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators.

Rui Xu, Sheng Ma, Yaohua Wang, Yang Guo

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Analysis of Single Events Effects on Supply-Regulated LC-Tank Voltage-Controlled Oscillator.

Xi Chen, Qian-cheng Guo, Hengzhou Yuan, Zhenyu Wu, Yang Guo

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

Lithography Hotspot Detection with FFT-based Feature Extraction and Imbalanced Learning Rate.

Xu He, Yu Deng, Shizhe Zhou, Rui Li, Yao Wang, Yang Guo

ACM Trans. Design Autom. Electr. Syst., 2020

A Dynamic and Proactive GPU Preemption Mechanism Using Checkpointing.

Chen Li, Andrew Zigerelli, Jun Yang, Youtao Zhang, Sheng Ma, Yang Guo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Novel Design Strategy Toward A2 Trojan Detection Based on Built-In Acceleration Structure.

Ding Deng, Yaohua Wang, Yang Guo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

AIM: Annealing in Memory for Vision Applications.

Zhi Wang, Xiao Hu, Jian Zhang, Zhao Lv, Yang Guo

Symmetry, 2020

Deviation based clustering for unsupervised person re-identification.

Munan Ning, Kaiwei Zeng, Yang Guo, Yaohua Wang

Pattern Recognit. Lett., 2020

Novel probability flipping method for ising annealing chip using circuit unreliability.

Zhi Wang, Yang Guo, Jian Zhang, Zhao Lv

Microelectron. J., 2020

Energy clustering for unsupervised person re-identification.

Kaiwei Zeng, Munan Ning, Yaohua Wang, Yang Guo

Image Vis. Comput., 2020

Configurable Ring Oscillator PUF Using Hybrid Logic Gates.

Ding Deng, Shen Hou, Zhenyu Wang, Yang Guo

IEEE Access, 2020

FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching.

Yaohua Wang, Lois Orosa, Xiangjun Peng, Yang Guo, Saugata Ghose, Minesh Patel, Jeremie S. Kim, Juan Gómez-Luna, Mohammad Sadrosadati, Nika Mansouri-Ghiasi, Onur Mutlu

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

A Macro-Micro Weakly-Supervised Framework for AS-OCT Tissue Segmentation.

Munan Ning, Cheng Bian, Donghuan Lu, Hong-Yu Zhou, Shuang Yu, Chenglang Yuan, Yang Guo, Yaohua Wang, Kai Ma, Yefeng Zheng

Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2020, 2020

CMSA: Configurable Multi-directional Systolic Array for Convolutional Neural Networks.

Rui Xu, Sheng Ma, Yaohua Wang, Yang Guo

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Maximum Clique Based Method for Optimal Solution of Pattern Classification.

Xu He, Yipei Wang, Zhiyong Fu, Yao Wang, Yang Guo

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Hierarchical Clustering With Hard-Batch Triplet Loss for Person Re-Identification.

Kaiwei Zeng, Munan Ning, Yaohua Wang, Yang Guo

Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

2019

Coordinated DMA: Improving the DRAM Access Efficiency for Matrix Multiplication.

Sheng Ma, Zhong Liu, Shenggang Chen, Libo Huang, Yang Guo, Zhiying Wang, Meidi Zhang

IEEE Trans. Parallel Distributed Syst., 2019

一种基于SAT求解器的组合电路重汇聚现象分析方法 (Reconvergence Phenomena Analysis Method in Combinational Circuits Based on SAT Solver).

Lujie Zhang, Chang Liu, Long Zhang, Yang Guo

计算机科学, 2019

A lightweight and secure-enhanced Strong PUF design on FPGA.

Shen Hou, Yang Guo, Shaoqing Li, Ding Deng, Yan Lei

IEICE Electron. Express, 2019

Priority-Based PCIe Scheduling for Multi-Tenant Multi-GPU Systems.

Chen Li, Jun Yang, Yifan Sun, Lingling Jin, Lingjie Xu, Zheng Cao, Pengfei Fan, David R. Kaeli, Sheng Ma, Yang Guo

IEEE Comput. Archit. Lett., 2019

28nm Fault-Tolerant Hardening-by-Design Frequency Divider for Reducing Soft Errors in Clock and Data Recovery.

Hengzhou Yuan, Yang Guo, Jianjun Chen, Yaqing Chi, Xi Chen, Bin Liang

IEEE Access, 2019

A Lightweight LFSR-Based Strong Physical Unclonable Function Design on FPGA.

Shen Hou, Yang Guo, Shaoqing Li

IEEE Access, 2019

An Efficient Direct Memory Access (DMA) Controller for Scientific Computing Accelerators.

Sheng Ma, Libo Huang, Yuanwu Lei, Yang Guo, Zhiying Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Load-Balanced Link Distribution in Mesh-Based Many-Core Systems.

Zicong Wang, Xiaowen Chen, Chen Li, Yang Guo, Man Liao, Zhong Liu

Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

Improving the DRAM Access Efficiency for Matrix Multiplication on Multicore Accelerators.

Sheng Ma, Yang Guo, Shenggang Chen, Libo Huang, Zhiying Wang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Framework for Memory Oversubscription Management in Graphics Processing Units.

Chen Li, Rachata Ausavarungnirun, Christopher J. Rossbach, Youtao Zhang, Onur Mutlu, Yang Guo, Jun Yang

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018

An SAT-Based Method to Multithreaded Program Verification for Mobile Crowdsourcing Networks.

Long Zhang, WanXia Qu, Yinjia Huo, Yang Guo, Sikun Li

Wirel. Commun. Mob. Comput., 2018

Detailed placement for pulse quenching enhancement in anti-radiation combinational circuit design.

Chang Liu, Xu He, Bin Liang, Yang Guo

Integr., 2018

VP-Router: On balancing the traffic load in on-chip networks.

Zicong Wang, Xiaowen Chen, Junyang Zhang, Yang Guo

IEICE Electron. Express, 2018

A task-based multi-core allocation mechanism for packet acceleration.

Zerun Li, Yang Guo, Sheng Liu, Junyang Zhang

IEICE Electron. Express, 2018

Cache Access Fairness in 3D Mesh-Based NUCA.

Zicong Wang, Xiaowen Chen, Zhonghai Lu, Yang Guo

IEEE Access, 2018

Analysis of SET Reconvergence and Hardening in the Combinational Circuit Using a SAT-Based Method.

Chang Liu, Long Zhang, Xu He, Yang Guo

IEEE Access, 2018

Performance Analysis of Different Convolution Algorithms in GPU Environment.

Rui Xu, Sheng Ma, Yang Guo

Proceedings of the 2018 IEEE International Conference on Networking, 2018

Adaptive VC Partitioning for NoCs in GPGPUs.

Sheng Ma, Hongyi Lu, Libo Huang, Li Shen, Yang Guo, Zhiying Wang, Wenliang Xue

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Accelerating CNNs Using Optimized Scheduling Strategy.

Rui Xu, Sheng Ma, Wenwu Li, Yang Guo

Proceedings of the Algorithms and Architectures for Parallel Processing, 2018

PEP: proactive checkpointing for efficient preemption on GPUs.

Chen Li, Andrew Zigerelli, Jun Yang, Yang Guo

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

A Formal Approach to Verify Parameterized Protocols in Mobile Cyber-Physical Systems.

Long Zhang, Wenyan Hu, WanXia Qu, Yang Guo, Sikun Li

Mob. Inf. Syst., 2017

A novel power-efficient IC test scheme.

Ding Deng, Xiaowen Chen, Yang Guo

IEICE Electron. Express, 2017

A Parallel Test Application Method towards Power Reduction.

Ding Deng, Yang Guo, Zhentao Li

J. Electron. Test., 2017

Fairness-oriented switch allocation for networks-on-chip.

Zicong Wang, Xiaowen Chen, Chen Li, Yang Guo

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Fairness-Oriented and Location-Aware NUCA for Many-Core SoC.

Zicong Wang, Xiaowen Chen, Chen Li, Yang Guo

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

A Radiation-Immune Low-Jitter High-Frequency PLL for SerDes.

Hengzhou Yuan, Jianjun Chen, Bin Liang, Yang Guo

Proceedings of the Computer Engineering and Technology - 21st CCF Conference, 2017

A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance.

Xu He, Yao Wang, Yang Guo, Sorin Cotofana

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A radiation hardened low-noise voltage-controlled-oscillator using negative feedback based multipath- current-releasing technology.

Hengzhou Yuan, Jianjun Chen, Bin Liang, Yang Guo

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A state recovery design against single-event transient in high-speed phase interpolation clock and data recovery circuit.

Jia-wei Tan, Yang Guo, Jianjun Chen, Hengzhou Yuan, Xi Chen

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement.

Xu He, Yao Wang, Yang Guo, Evangeline F. Y. Young

ACM Trans. Design Autom. Electr. Syst., 2016

A low-jitter self-biased phase-locked loop for SerDes.

Hengzhou Yuan, Yang Guo, Yao Liu, Bin Liang, Qian-cheng Guo, Jia-wei Tan

Proceedings of the International SoC Design Conference, 2016

DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture.

Chen Li, Sheng Ma, Lu Wang, Zicong Wang, Xia Zhao, Yang Guo

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Overcoming and Analyzing the Bottleneck of Interposer Network in 2.5D NoC Architecture.

Chen Li, Zicong Wang, Lu Wang, Sheng Ma, Yang Guo

Proceedings of the Advanced Computer Architecture - 11th Conference, 2016

2015

Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips.

Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Shenggang Chen, Hu Chen, Man Liao

J. Softw., 2015

Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.

Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Shenggang Chen, Hu Chen

J. Electr. Comput. Eng., 2015

Express Ring: a multi-layer and non-blocking NoC architecture.

Chen Li, Sheng Ma, Shenggang Chen, Yang Guo, Peng Wang

IEICE Electron. Express, 2015

Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.

Xiaowen Chen, Zhonghai Lu, Yang Li, Axel Jantsch, Xueqian Zhao, Shuming Chen, Yang Guo, Zonglin Liu, Jianzhuang Lu, Jianghua Wan, Shuwei Sun, Shenggang Chen, Hu Chen

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Equivalence checking of scheduling in high-level synthesis.

Tun Li, Jian Hu, Yang Guo, Sikun Li, QingPing Tan

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

An effective analytical 3D placer in monolithic 3D IC designs.

Yande Jiang, Xu He, Chang Liu, Yang Guo

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

An efficient floating-point multiplier for digital signal processors.

Zonglin Liu, Sheng Ma, Yang Guo

IEICE Electron. Express, 2014

Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs.

Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Hengzhu Liu

IEICE Electron. Express, 2014

A 40nm/65nm process adaptive low jitter phase-locked loop.

Hengzhou Yuan, Yang Guo, Zhuo Ma

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013

Efficient translation validation of high-level synthesis.

Tun Li, Yang Guo, Wanwei Liu, Chiyuan Ma

Proceedings of the International Symposium on Quality Electronic Design, 2013

Translation validation of scheduling in high level synthesis.

Tun Li, Yang Guo, Wanwei Liu, Mingsheng Tang

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Application specified soft error failure rate analysis using sequential equivalence checking techniques.

Tun Li, Dan Zhu, Sikun Li, Yang Guo

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

An adaptive multi-modulus frequency divider.

Hengzhou Yuan, Zhuo Ma, Yang Guo

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

State space reduction in modeling checking parameterized cache coherence protocol by two-dimensional abstraction.

Yang Guo, WanXia Qu, Long Zhang, Weixia Xu

J. Supercomput., 2012

A novel parallel memory organization supporting multiple access types with matched memory modules.

Sheng Liu, Shuming Chen, Hu Chen, Yang Guo

IEICE Electron. Express, 2012

2008

2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions.

Dan Zhu, Tun Li, Yang Guo, Sikun Li

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Explicit Model Checking Based on Integer Pointer and Fibonacci Hash.

WanXia Qu, Tun Li, Yang Guo, Xiaodong Yang

Proceedings of the 9th International Conference for Young Computer Scientists, 2008

Efficient Verification of Parameterized Cache Coherence Protocols.

Wanxia Qu, Yang Guo, Zhengbin Pang, Xiaodong Yang

Proceedings of the 9th International Conference for Young Computer Scientists, 2008

2007

Experiences Teaching Functional Verification Techniques with Practical Designs.

Tun Li, Yang Guo, Sikun Li, Wei Dong, Rangyu Deng

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

A Novel Collaborative Verification Environment for SoC Co-Verification.

Tun Li, Sikun Li, Jinshan Yu, Yang Guo

Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, 2007

Coverage Driven Test Generation Framework for RTL Functional Verification.

Yang Guo, WanXia Qu, Tun Li, Sikun Li

Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

2006

Scheduling of Transactions Based on Extended Scheduling Timed Petri Nets for SoC System-Level Test-Case Generation.

Jinshan Yu, Tun Li, Yang Guo, QingPing Tan

Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006

2005

Applying Constraint Logic Programming to Predicate Abstraction of RTL Verilog Descriptions.

Tun Li, Yang Guo, Sikun Li, Dan Zhu

Proceedings of the MICAI 2005: Advances in Artificial Intelligence, 2005

MA2TG: A Functional Test Program Generator for Microprocessor Verification.

Tun Li, Dan Zhu, Yang Guo, GongJie Liu, Sikun Li

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming.

Tun Li, Yang Guo, GongJie Liu, Sikun Li

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming.

Tun Li, Yang Guo, Sikun Li, GongJie Liu

Proceedings of the Automated Technology for Verification and Analysis, 2005

Automatic functional test program generation for microprocessor verification.

Tun Li, Dan Zhu, Lei Liang, Yang Guo, Sikun Li

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Automatic Circuit Extractor for HDL Description Using Program Slicing.

Tun Li, Yang Guo, Sikun Li

J. Comput. Sci. Technol., 2004

Design and Implementation of a Parallel Verilog Simulator: PVSim.

Tun Li, Yang Guo, Sikun Li

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Assertion-based automated functional vectors generation using constraint logic programming.

Tun Li, Yang Guo, Sikun Li

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

CLP Based Static Property Checking.

Tun Li, Yang Guo, Sikun Li

Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004

Parallel verilog simulation: architecture and circuit partition.

Tun Li, Yang Guo, Sikun Li, Fujiang Ao, Gongjie Li

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

An Automatic Circuit Extractor for RTL Verification.

Tun Li, Yang Guo, Sikun Li

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003