Giovanni Mariani

Orcid: 0009-0005-4501-2018

According to our database1, Giovanni Mariani authored at least 53 papers between 2007 and 2025.

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Bibliography

2025
Evaluation of an Experimental Procedure to Calibrate In Situ an Instrumented Glove for Measuring Biomechanical Overloads.
IEEE Trans. Instrum. Meas., 2025

Transparency Evaluation of SIDE Exoskeleton: A Preliminary Study for Haptic VR Training.
Proceedings of the IEEE International Symposium on Medical Measurements and Applications, 2025

2022
Design and characterization of a smart fabric sensor to recognize human intention for robotic applications.
Proceedings of the IEEE International Workshop on Metrology for Industry 4.0 & IoT, 2022

RANK - Robotic Ankle: Design and testing on irregular terrains.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022

2021
Efficient image dataset classification difficulty estimation for predicting deep-learning accuracy.
Vis. Comput., 2021

Distilling Optimal Neural Networks: Rapid Search in Diverse Spaces.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

2020
Mixed-precision deep learning based on computational memory.
CoRR, 2020

BEAT: Balance Evaluation Automated Testbed for the standardization of balance assessment in human wearing exoskeleton.
Proceedings of the 2020 IEEE International Workshop on Metrology for Industry 4.0 & IoT, 2020

Evolutionary Algorithm with Non-parametric Surrogate Model for Tensor Program optimization.
Proceedings of the IEEE Congress on Evolutionary Computation, 2020

2019
FloatX: A C++ Library for Customized Floating-Point Arithmetic.
ACM Trans. Math. Softw., 2019

NeuNetS: An Automated Synthesis Engine for Neural Network Design.
CoRR, 2019

NAPEL: Near-Memory Computing Application Performance Prediction via Ensemble Learning.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

TAPAS: Train-Less Accuracy Predictor for Architecture Search.
Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019

2018
Analytic Multi-Core Processor Model for Fast Design-Space Exploration.
IEEE Trans. Computers, 2018

Predicting cloud performance for HPC applications before deployment.
Future Gener. Comput. Syst., 2018

BAGAN: Data Augmentation with Balancing GAN.
CoRR, 2018

2017
Classification of thread profiles for scaling application behavior.
Parallel Comput., 2017

MeSAP: A fast analytic power model for DRAM memories.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Predicting Cloud Performance for HPC Applications: a User-oriented Approach.
Proceedings of the 17th IEEE/ACM International Symposium on Cluster, 2017

2016
COBAYN: Compiler Autotuning Framework Using Bayesian Networks.
ACM Trans. Archit. Code Optim., 2016

Scaling Properties of Parallel Applications to Exascale.
Int. J. Parallel Program., 2016

2015
DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Analytic processor model for fast design-space exploration.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Scaling application properties to exascale.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

An instrumentation approach for hardware-agnostic software characterization.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014
A Bayesian network approach for compiler auto-tuning for embedded processors.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

DRuiD: Designing reconfigurable architectures with decision-making support.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Design-space exploration and runtime resource management for multicores.
ACM Trans. Embed. Comput. Syst., 2013

ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models.
Parallel Comput., 2013

Run-time optimization of a dynamically reconfigurable embedded system through performance prediction.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
OSCAR: An Optimization Methodology Exploiting Spatial Correlation in Multicore Design Spaces.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework.
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

2011
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration.
IET Comput. Digit. Tech., 2011

ARTE: An Application-specific Run-Time management framework for multi-core systems.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011


Optimization Algorithms for Design Space Exploration of Embedded Systems.
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

Response Surface Modeling for Design Space Exploration of Embedded System.
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming.
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

Design Space Exploration of Parallel Architectures.
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

Design Space Exploration Supporting Run-Time Resource Management.
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

2010

An industrial design space exploration framework for supporting run-time resource management on multi-core systems.
Proceedings of the Design, Automation and Test in Europe, 2010

A correlation-based design space exploration methodology for multi-processor systems-on-chip.
Proceedings of the 47th Design Automation Conference, 2010

Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors.
Proceedings of the ARCS '10, 2010

An Efficient Run-Time Management Methodology for Stereo Matching Application.
Proceedings of the ARCS '10, 2010

2009
A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2007
A topology design customization approach for STNoC.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Application-Specific Topology Design Customization for STNoC.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Mapping and Topology Customization Approaches for Application-Specific STNoC Designs.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007


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