Hillery C. Hunter

According to our database, Hillery C. Hunter authored at least 21 papers between 2000 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2020

Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem.

Saravanan Sethuraman, Venkata Kalyan Tavva, Karthick Rajamani, Chitra K. Subramanian, Kyu-Hyoun Kim, Hillery C. Hunter, M. B. Srinivas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019

BlueConnect: Decomposing all-reduce for deep learning on heterogeneous network hierarchy.

Minsik Cho, Ulrich Finkler, Mauricio J. Serrano, David S. Kung, Hillery C. Hunter

IBM J. Res. Dev., 2019

BlueConnect: Decomposing All-Reduce for Deep Learning on Heterogeneous Network Hierarchy.

Minsik Cho, Ulrich Finkler, David S. Kung, Hillery C. Hunter

Proceedings of Machine Learning and Systems 2019, 2019

2018

PANEL: Open panel and discussion on tackling complexity, reproducibility and tech transfer challenges in a rapidly evolving AI/ML/systems research.

Grigori Fursin, Thierry Moreau, Hillery C. Hunter, Yiran Chen, Charles Qi, Tianqi Chen

Proceedings of the 1st on Reproducible Quality-Efficient Systems Tournament on Co-designing Pareto-efficient Deep Learning, 2018

2015

Guest Editorial Computing in Emerging Technologies (Second Issue).

Saibal Mukhopadhyay, Swarup Bhunia, Hillery C. Hunter, Kaushik Roy

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

2014

Guest Editorial Computing in Emerging Technologies (First Issue).

Saibal Mukhopadhyay, Swarup Bhunia, Hillery C. Hunter, Kaushik Roy

IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Adapting Server Systems for New Memory Technologies.

Hillery C. Hunter, Luis Alfonso Lastras-Montaño, Bishwaranjan Bhattacharjee

Computer, 2014

2013

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems.

Janani Mukundan, Hillery C. Hunter, Kyu-Hyoun Kim, Jeffrey Stuecheli, José F. Martínez

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2011

Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue.

Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John

IEEE Micro, 2011

2010

Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory.

Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. Hunter, Lizy K. John

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

The virtual write queue: coordinating DRAM and last-level cache policies.

Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009

Hardware-compiler co-design for adjustable data power savings.

Hillery C. Hunter, Erik M. Nystrom, Daniel A. Connors, Wen-mei W. Hwu

Microprocess. Microsystems, 2009

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.

Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2009

2008

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.

John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer

IEEE J. Solid State Circuits, 2008

2007

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.

John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2004

Matching on -Chip Data Storage to Telecommunication and Media Application Properties

Hillery C. Hunter

PhD thesis, 2004

2003

An innovative low-power high-performance programmable signal processor for digital communications.

Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter

IBM J. Res. Dev., 2003

A new look at exploiting data parallelism in embedded systems.

Hillery C. Hunter, Jaime H. Moreno

Proceedings of the International Conference on Compilers, 2003

2002

Code coverage and input variability: effects on architecture and compiler research.

Hillery C. Hunter, Wen-mei W. Hwu

Proceedings of the International Conference on Compilers, 2002

2001

Enhancing loop buffering of media and telecommunications applications using low-overhead predication.

John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

2000

Hardware Support for Dynamic Management of Compiler-Directed Computation Reuse.

Daniel A. Connors, Hillery C. Hunter, Ben-Chung Cheng, Wen-mei W. Hwu

Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000