Pedro López
Orcid: 0000-0003-4544-955XAffiliations:
- Universitat Politècnica de València, Spain
According to our database1,
Pedro López
authored at least 144 papers
between 1993 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Future Gener. Comput. Syst., 2023
2022
CoRR, 2022
The DeepHealth Toolkit: A Key European Free and Open-Source Software for Deep Learning and Computer Vision Ready to Exploit Heterogeneous HPC and Cloud Architectures.
Proceedings of the Technologies and Applications for Big Data Value, 2022
2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
2019
ACM Trans. Archit. Code Optim., 2019
J. Parallel Distributed Comput., 2019
2018
J. Parallel Distributed Comput., 2018
Proceedings of the 4th IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era, 2018
2017
Parallel Comput., 2017
J. Parallel Distributed Comput., 2017
A fault-tolerant routing strategy for <i>k</i>-ary <i>n</i>-direct <i>s</i>-indirect topologies based on intermediate nodes.
Concurr. Comput. Pract. Exp., 2017
2016
IEEE Trans. Parallel Distributed Syst., 2016
The k-ary n-direct s-indirect family of topologies for large-scale interconnection networks.
J. Supercomput., 2016
Future Gener. Comput. Syst., 2016
Proceedings of the 2nd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era HiPINEB@HPCA 2016, 2016
2015
J. Supercomput., 2015
Parallel Comput., 2015
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015
Using GPU and SIMD Implementations to Improve Performance of Robotic Emotional Processes.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014
2013
Hardware-Based Generation of Independent Subtraces of Instructions in Clustered Processors.
IEEE Trans. Computers, 2013
Proceedings of the International Conference on Computational Science, 2013
Proceedings of the Euro-Par 2013 Parallel Processing, 2013
Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2012
A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions.
IEEE Trans. Parallel Distributed Syst., 2012
IEEE Trans. Parallel Distributed Syst., 2012
Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches.
IEEE Trans. Computers, 2012
IEEE Trans. Computers, 2012
Combining recency of information with selective random and a victim cache in last-level caches.
ACM Trans. Archit. Code Optim., 2012
Proceedings of the 11th IEEE International Symposium on Network Computing and Applications, 2012
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012
2011
Proceedings of the Encyclopedia of Parallel Computing, 2011
Concurr. Comput. Pract. Exp., 2011
Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
Proceedings of the 18th Euromicro Conference on Parallel, 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
FT<sup>2</sup>EI: A Dynamic Fault-Tolerant Routing Methodology for Fat Trees with Exclusion Intervals.
IEEE Trans. Parallel Distributed Syst., 2009
IEEE Trans. Computers, 2009
Intell. Autom. Soft Comput., 2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Boosting single-thread performance in multi-core systems through fine-grain multi-threading.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the Euro-Par 2009 Parallel Processing, 2009
An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the PACT 2009, 2009
2008
IEEE Comput. Archit. Lett., 2008
Proceedings of the 16th Euromicro International Conference on Parallel, 2008
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008
Proceedings of the Euro-Par 2008, 2008
On the Influence of the Packet Marking and Injection Control Schemes in Congestion Management for MINs.
Proceedings of the Euro-Par 2008, 2008
2007
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007
Proceedings of the 15th Euromicro International Conference on Parallel, 2007
Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips.
Proceedings of the First International Symposium on Networks-on-Chips, 2007
An Efficient Fault-Tolerant Routing Methodology for Fat-Tree Interconnection Networks.
Proceedings of the Parallel and Distributed Processing and Applications, 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Proceedings of the 2007 International Conference on Intelligent Pervasive Computing, 2007
Proceedings of the High Performance Computing and Communications, 2007
VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007
2006
IEEE Trans. Computers, 2006
Scalable Comput. Pract. Exp., 2006
J. Parallel Distributed Comput., 2006
Proceedings of the 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006
Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2006
2005
IEEE Trans. Parallel Distributed Syst., 2005
J. Parallel Distributed Comput., 2005
A Memory-Effective Fault-Tolerant Routing Strategy for Direct Interconnection Networks.
Proceedings of the 4th International Symposium on Parallel and Distributed Computing (ISPDC 2005), 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
2004
IEEE Comput. Archit. Lett., 2004
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2004
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Proceedings of the 33rd International Conference on Parallel Processing (ICPP 2004), 2004
Proceedings of the 10th International Conference on Parallel and Distributed Systems, 2004
Proceedings of the High Performance Computing, 2004
Reducing Power Consumption in Interconnection Networks by Dynamically Adjusting Link Width.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004
2003
FC3D: Flow Control-Based Distributed Deadlock Detection Mechanism for True Fully Adaptive Routing in Wormhole Networks.
IEEE Trans. Parallel Distributed Syst., 2003
Applying In-Transit Buffers to Boost the Performance of Networks with Source Routing.
IEEE Trans. Computers, 2003
Proceedings of the 11th Euromicro Workshop on Parallel, 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003
Low-Fragmentation Mapping Strategies for Linear Forwarding Tables in InfiniBand<sup>TM</sup>.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003
Proceedings of the Euro-Par 2003. Parallel Processing, 2003
2002
IEEE Trans. Parallel Distributed Syst., 2002
Proceedings of the 10th Euromicro Workshop on Parallel, 2002
Proceedings of the 10th Euromicro Workshop on Parallel, 2002
Proceedings of the High Performance Computing, 4th International Symposium, 2002
Proceedings of the High Performance Computing, 4th International Symposium, 2002
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002
Proceedings of the Euro-Par 2002, 2002
Proceedings of the Euro-Par 2002, 2002
2001
IEEE Trans. Parallel Distributed Syst., 2001
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001
Improving Network Performance by Reducing Network Contention in Source-Based COWs with a Low Path-Computation Overhead.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001
Proceedings of the 2001 International Conference on Parallel Processing, 2001
2000
On the Influence of the Selection Function on the Performance of Networks of Workstations.
Proceedings of the High Performance Computing, Third International Symposium, 2000
Combining In-Transit Buffers with Optimized Routing Schemes to Boost the Performance of Networks with Source Routing.
Proceedings of the High Performance Computing, Third International Symposium, 2000
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000
Performance evaluation of a new routing strategy for irregular networks with source routing.
Proceedings of the 14th international conference on Supercomputing, 2000
Proceedings of the 2000 International Conference on Parallel Processing, 2000
1999
Proceedings of the Seventh Euromicro Workshop on Parallel and Distributed Processing. PDP'99, 1999
Performance Evaluation of Networks of Workstations with Hardware Shared Memory Model Using Execution-Driven Simulation.
Proceedings of the International Conference on Parallel Processing 1999, 1999
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999
1998
J. Syst. Archit., 1998
Proceedings of the 1998 workshop on Computer architecture education, 1998
DRIL: Dynamically Reduced Message Injection Limitation Mechanism for Wormhole Networks.
Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998
Proceedings of the Computer Performance Evaluation: Modelling Techniques and Tools, 1998
1997
On the Reduction of Deadlock Frequency by Limiting Message Injection in Wormhole Networks.
Proceedings of the Parallel Computer Routing and Communication, 1997
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997
Software-Based Deadlock Recovery Technique for True Fully Adaptive Routing in Wormhole Networks.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997
Proceedings of the Fourth International on High-Performance Computing, 1997
Proceedings of the Communication and Architectural Support for Network-Based Parallel Computing, 1997
1996
Interconnection Network Design: A Statistical Analysis of Interactions between Factors.
Proceedings of the 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996
Proceedings of the 1996 International Conference on Parallel Processing, 1996
1995
Comput. Artif. Intell., 1995
1994
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994
Proceedings of the Parallel Computer Routing and Communication, 1994
Proceedings of the Workshop on Interconnection Networks and Mapping and Scheduling Parallel Computations, 1994
1993
Deadlock-Free Adaptive Routing Algorithms for the 3D-Torus: Limitations and Solutions.
Proceedings of the PARLE '93, 1993