Visvesh S. Sathe
Affiliations:- University of Washington, Department of Electrical and Computer Engineering, Seattle, WA, USA
- University of Michigan, Ann Arbor, MI, USA (Ph.D.)
- AMD, Santa Clara, CA, USA (2007-2013)
According to our database1,
Visvesh S. Sathe
authored at least 62 papers
between 2003 and 2024.
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Bibliography
2024
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, January, 2024
2023
Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains.
IEEE J. Solid State Circuits, 2023
2022
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control.
IEEE J. Solid State Circuits, 2022
An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS.
Proceedings of the IEEE International Conference on RFID, 2022
An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A 0.0023 mm<sup>2</sup>/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression.
IEEE Trans. Biomed. Circuits Syst., 2020
A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS.
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
An All-Digital Fused PLL-Buck Architecture for 82% Average V<sub>dd</sub>-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor.
IEEE J. Solid State Circuits, 2019
A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation.
IEEE J. Solid State Circuits, 2019
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains.
IEEE J. Solid State Circuits, 2019
A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems.
IEEE J. Solid State Circuits, 2018
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 Analog Front End With Reduced ADC Resolution Requirements.
IEEE Trans. Biomed. Circuits Syst., 2016
Introduction to the Special Section on the 2015 Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Regenerative Breaking: Recovering Stored Energy from Inactive Voltage Domains for Energy-efficient Systems-on-Chip.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
All-digital hybrid-control buck converter for Integrated Voltage Regulator applications.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
2014
Quasi-resonant clocking: a run-time control approach for true voltage-frequency-scalability.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
A deterministic-dither-based, all-digital system for on-chippower supply noise measurement.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
2013
IEEE J. Solid State Circuits, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2010
A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm<sup>2</sup> at 81% efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the Second Conference on Computing Frontiers, 2005
2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003