Hankyu Chi

According to our database¹, Hankyu Chi authored at least 14 papers between 2010 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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On csauthors.net:

Bibliography

2025

22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

ML-Based Fast and Accurate Performance Modeling and Prediction for High-Speed Memory Interfaces Across Different Technologies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2025

A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

WITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth Memory.

[BibT_eX]

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2021

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

2020

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2020

2019

A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2017

29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2010

A clock synchronization system with IEEE 1588-2008 adapters over existing Gigabit Ethernet equipment.

[BibT_eX]

[DOI]

Jiho Han

Hankyu Chi

Deog-Kyoon Jeong

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Hankyu Chi

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