Louis Hutin

Orcid: 0000-0001-6429-3867

According to our database1, Louis Hutin authored at least 18 papers between 2013 and 2026.

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Bibliography

2026
A Low-Power Bayesian Head Using SOT-MRAM Arrays for Uncertainty-Aware Binary Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025
Intrinsic Annealing in a Hybrid Memristor-Magnetic Tunnel Junction Ising Machine.
CoRR, June, 2025

Optimizing RF Readout for Silicon Spin Qubits in an Access Array.
IEEE Trans. Instrum. Meas., 2025

2024
Roadmap to Neuromorphic Computing with Emerging Technologies.
CoRR, 2024

Optimizing with phases: design and application space assessment for networks of phase-locked Ring Oscillators.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

RF performance of Standard, High-Resistivity and Trap-Rich Silicon substrates down to cryogenic temperature.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022
Electrical Coupling of Perpendicular Superparamagnetic Tunnel Junctions for Probabilistic Computing.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

1024 3D-Stacked Monolithic NEMS Array with 375μm<sup>2</sup>0.5mW 0.28ppm Frequency Deviation Pixel-level Readout for Zeptogram Gravimetric Sensing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
MOS technology for quantum computing: recent progress and perspectives for scaling up.
Proceedings of the Device Research Conference, 2021

2018

Compact MEMS modeling to design full adder in Capacitive Adiabatic Logic.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

Towards a scalable quantum computer.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018


2017
Capacitive adiabatic logic based on gap-closing MEMS devices.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Design considerations for optimization of pull-in stability margin in electrostatic N/MEM relays.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

SOI CMOS technology for quantum information processing.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

2013
Relays do not leak: CMOS does.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013


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