Charlotte Frenkel
Orcid: 0000-0002-1879-0288Affiliations:
- Delft University of Technology, The Netherlands
According to our database1,
Charlotte Frenkel
authored at least 43 papers
between 2015 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
CoRR, August, 2025
Chameleon: A MatMul-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data.
CoRR, May, 2025
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2025
An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Weight/Output Stationarity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
TESS: A Scalable Temporally and Spatially Local Learning Rule for Spiking Neural Networks.
Proceedings of the International Joint Conference on Neural Networks, 2025
2024
ACM Trans. Embed. Comput. Syst., May, 2024
Adaptive Robotic Arm Control with a Spiking Recurrent Neural Network on a Digital Accelerator.
CoRR, 2024
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2024
Active Dendrites Enable Efficient Continual Learning in Time-To-First-Spike Neural Networks.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2023
Editorial: Focus issue on energy-efficient neuromorphic devices, systems and algorithms.
Neuromorph. Comput. Eng., December, 2023
Bottom-Up and Top-Down Approaches for the Design of Neuromorphic Processing Systems: Tradeoffs and Synergies Between Natural and Artificial Intelligence.
Proc. IEEE, June, 2023
NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking.
CoRR, 2023
Exploring Information-Theoretic Criteria to Accelerate the Tuning of Neuromorphic Level-Crossing ADCs.
Proceedings of the Neuro-Inspired Computational Elements Conference, 2023
Event-based Classification with Recurrent Spiking Neural Networks on Low-end Micro-Controller Units.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
SPAIC: A sub-μW/Channel, 16-Channel General-Purpose Event-Based Analog Front-End with Dual-Mode Encoders.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
THOR - A Neuromorphic Processor with 7.29G TSOP$^2$/mm$^2$Js Energy-Throughput Efficiency.
CoRR, 2022
ReckOn: A 28nm Sub-mm2 Task-Agnostic Spiking Recurrent Neural Network Processor Enabling On-Chip Learning over Second-Long Timescales.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 120dB Programmable-Range On-Chip Pulse Generator for Characterizing Ferroelectric Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Stochastic dendrites enable online learning in mixed-signal neuromorphic processing systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Spiking Neural Network Integrated Circuits: A Review of Trends and Future Directions.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Biologically-inspired training of spiking recurrent neural networks with neuromorphic hardware.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode.
IEEE J. Solid State Circuits, 2021
Online Training of Spiking Recurrent Neural Networks with Phase-Change Memory Synapses.
CoRR, 2021
Bottom-Up and Top-Down Neural Processing Systems Design: Neuromorphic Intelligence as the Convergence of Natural and Artificial Intelligence.
CoRR, 2021
PCM-Trace: Scalable Synaptic Eligibility Traces with Resistivity Drift of Phase-Change Materials.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Bottom-up and top-down neuromorphic processor design: Unveiling roads to embedded cognition.
PhD thesis, 2020
A 28-nm Convolutional Neuromorphic Processor Enabling Online Learning with Spike-Based Retinas.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A 0.086-mm<sup>2</sup> 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS.
IEEE Trans. Biomed. Circuits Syst., 2019
MorphIC: A 65-nm 738k-Synapse/mm<sup>2</sup> Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning.
IEEE Trans. Biomed. Circuits Syst., 2019
Learning without feedback: Direct random target projection as a feedback-alignment algorithm with layerwise feedforward training.
CoRR, 2019
A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 65-nm 738k-Synapse/mm<sup>2</sup> Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
A 0.086-mm<sup>2</sup> 9.8-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28nm CMOS.
CoRR, 2018
2017
SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping.
IEEE J. Solid State Circuits, 2017
A fully-synthesized 20-gate digital spike-based synapse with embedded online learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
2015
A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015