Jongsun Park

According to our database1, Jongsun Park authored at least 92 papers between 2000 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
An Energy-Quality Scalable STDP Based Sparse Coding Processor With On-Chip Learning Capability.
IEEE Trans. Biomed. Circuits Syst., 2020

Rank order coding based spiking convolutional neural network architecture with energy-efficient membrane voltage updates.
Neurocomputing, 2020

Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers.
IEEE Access, 2020

Prediction Confidence based Low Complexity Gradient Computation for Accelerating DNN Training.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Spike Counts Based Low Complexity SNN Architecture With Binary Synapse.
IEEE Trans. Biomed. Circuits Syst., 2019

Compact Implementations of HIGHT Block Cipher on IoT Platforms.
Secur. Commun. Networks, 2019

Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply-Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

A Perspective on Test Methodologies for Supervised Machine Learning Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Design of Processing-"Inside"-Memory Optimized for DRAM Behaviors.
IEEE Access, 2019

An Energy-efficient On-chip Learning Architecture for STDP based Sparse Coding.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Energy Efficient Canny Edge Detector for Advanced Mobile Vision Applications.
IEEE Trans. Circuits Syst. Video Technol., 2018

A Low-Latency and Area-Efficient Gram-Schmidt-Based QRD Architecture for MIMO Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Mosaic-CNN: A Combined Two-Step Zero Prediction Approach to Trade off Accuracy and Computation Energy in Convolutional Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions.
IEEE Access, 2018

Low Cost Convolutional Neural Network Accelerator Based on Bi-Directional Filtering and Bit-Width Reduction.
IEEE Access, 2018

Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme.
Proceedings of the International SoC Design Conference, 2018

Low Cost Hardware Implementation of LEA-128 Encryption using Bit-Serial Technique.
Proceedings of the International SoC Design Conference, 2018

Spin Orbit Torque Device based Stochastic Multi-bit Synapses for On-chip STDP Learning.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Charge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Spike Counts Based Low Complexity Learning with Binary Synapse.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

Content addressable memory based binarized neural network accelerator using time-domain signal processing.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Novel Folded-KES Architecture for High-Speed and Area-Efficient BCH Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Improved Perturbation Vector Generation Method for Accurate SRAM Yield Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Replacing eFlash with STTRAM in IoTs: Security Challenges and Solutions.
J. Hardw. Syst. Secur., 2017

Adaptive ECC for Tailored Protection of Nanoscale Memory.
IEEE Des. Test, 2017

An efficient convolutional neural networks design with heterogeneous SRAM cell sizing.
Proceedings of the International SoC Design Conference, 2017

Bit-width reduction and customized register for low cost convolutional neural network accelerator.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

A DRAM based physical unclonable function capable of generating >10<sup>32</sup> Challenge Response Pairs per 1Kbit array for secure chip authentication.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A 0.4-mW, 4.7-ps Resolution Single-Loop ΔΣ TDC Using a Half-Delay Time Integrator.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Wearables, Implants, and Internet of Things: The Technology Needs in the Evolving Landscape.
IEEE Trans. Multi Scale Comput. Syst., 2016

Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Overview of Circuits, Systems, and Applications of Spintronics.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Customized SRAM design for low power video code applications.
Proceedings of the International SoC Design Conference, 2016

Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

A compact multi-mode CORDIC with Global-Shifting-Sum (GSS) method.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Guest Editors' Introduction: Wearables, Implants, and Internet of Things.
IEEE Trans. Multi Scale Comput. Syst., 2015

D<sup>2</sup>ART: Direct Data Accessing from Passive RFID Tag for infra-less, contact-less, and battery-less pervasive computing.
Microprocess. Microsystems, 2015

A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder.
IEEE J. Solid State Circuits, 2015

A hybrid multimode BCH encoder architecture for area efficient re-encoding approach.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Self-correcting STTRAM under magnetic field attacks.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Domain wall memory based digital signal processors for area and energy-efficiency.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks.
IEEE Trans. Very Large Scale Integr. Syst., 2014

VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

An Efficient Memory-Address Remapping Technique for High-Throughput QC-LDPC Decoder.
Circuits Syst. Signal Process., 2014

A low-complexity composite QR decomposition architecture for MIMO detector.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System.
J. Signal Process. Syst., 2013

Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Design of Wavelet-Based ECG Detector for Implantable Cardiac Pacemakers.
IEEE Trans. Biomed. Circuits Syst., 2013

Reconfigurable ECC for adaptive protection of memory.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Multidimensional Householder based high-speed QR decomposition architecture for MIMO receivers.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Resource Efficient Implementation of Low Power MB-OFDM PHY Baseband Modem With Highly Parallel Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

Heterogeneous SRAM Cell Sizing for Low-Power H.264 Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

High-speed tournament givens rotation-based QR Decomposition Architecture for MIMO Receiver.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Dual queue based rate selecting schedule for throughput enhancement in WLANs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Jitter and Power Analysis on DCO.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

An Energy Efficient V<sub>PP</sub> Generator With Fast Ramp-Up Time for Mobile DRAM.
IEEE J. Solid State Circuits, 2011

Low-power programmable divider with a shared counter for frequency synthesiser.
IET Circuits Devices Syst., 2011

Improved MIMO SIC Detection Exploiting ML Criterion.
Proceedings of the 74th IEEE Vehicular Technology Conference, 2011

2010
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering.
J. Signal Process. Syst., 2010

Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Energy Efficient Hardware Architecture of LU Triangularization for MIMO Receiver.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Hydrogen passivation effects under negative bias temperature instability stress in metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon capacitors for flash memories.
Microelectron. Reliab., 2010

Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling.
IET Circuits Devices Syst., 2010

ProMINoC: An efficient Network-on-Chip design for flexible data permutation.
IEICE Electron. Express, 2010

2009
A packet forwarding controller for mobile IP-based networks with packet buffering.
IEEE Trans. Consumer Electron., 2009

A distributed MAC design for data collision-free wireless USB home networks.
IEEE Trans. Consumer Electron., 2009

A fair distributed resource allocation method in UWB wireless PANs with WiMedia MAC.
J. Commun. Networks, 2009

Enhancing Location Estimation and Reducing Computation using Adaptive Zone Based K-NNSS Algorithm.
KSII Trans. Internet Inf. Syst., 2009

Soft MIMO ML demodulation based on bitwise constellation partitioning.
IEEE Commun. Lett., 2009

2008
A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption.
J. Signal Process. Syst., 2008

2006
Efficient modeling of 1/f<sup>alpha</sup>/ noise using multirate process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2004
Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

A low power reconfigurable DCT architecture to trade off image quality for computational complexity.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
High-performance FIR filter design based on sharing multiplication.
IEEE Trans. Very Large Scale Integr. Syst., 2003

2002
High performance and low power FIR filter design based on sharing multiplication.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Low power reconfigurable DCT design based on sharing multiplication.
Proceedings of the IEEE International Conference on Acoustics, 2002

2000
Non-adaptive and adaptive filter implementation based on sharing multiplication.
Proceedings of the IEEE International Conference on Acoustics, 2000


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