Saurabh Sinha

Orcid: 0000-0001-7453-9576

Affiliations:
  • ARM Inc., Austin, TX, USA


According to our database1, Saurabh Sinha authored at least 67 papers between 1998 and 2022.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor.
CoRR, 2021

3D-Split SRAM: Enabling Generational Gains in Advanced CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
Thermal Analysis of a 3D Stacked High-Performance Commercial Microprocessor using Face-to-Face Wafer Bonding Technology.
CoRR, 2020

Stack up your chips: Betting on 3D integration to augment Moore's Law scaling.
CoRR, 2020

Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

2019
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Enhanced 3D Implementation of an Arm<sup>®</sup> Cortex<sup>®</sup>-A Microprocessor.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018
Standard Cell Library Design and Optimization Methodology for ASAP7 PDK.
CoRR, 2018

Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Impact of FinFET on Near-Threshold Voltage Scalability.
IEEE Des. Test, 2017

Frequency and time domain analysis of power delivery network for monolithic 3D ICs.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
ASAP7: A 7-nm finFET predictive process design kit.
Microelectron. J., 2016

Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches.
IET Comput. Digit. Tech., 2016

Lessons from the tech transfer trenches.
Commun. ACM, 2016

Monolithic 3D IC design: Power, performance, and area impact at 7nm.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Match-making for monolithic 3D IC: finding the right technology node.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Circuit design perspectives for Ge FinFET at 10nm and beyond.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Power benefit study of monolithic 3D IC at the 7nm technology node.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Test Generation from Business Rules.
Proceedings of the 8th IEEE International Conference on Software Testing, 2015

Automated Modularization of GUI Test Cases.
Proceedings of the 37th IEEE/ACM International Conference on Software Engineering, 2015

2014
Global software testing under deadline pressure: Vendor-side experiences.
Inf. Softw. Technol., 2014

Robust test automation using contextual clues.
Proceedings of the International Symposium on Software Testing and Analysis, 2014

Physical design and FinFETs.
Proceedings of the International Symposium on Physical Design, 2014

Operational abstractions of model transforms.
Proceedings of the 7th India Software Engineering Conference, Chennai, 2014

Software services: a research roadmap.
Proceedings of the on Future of Software Engineering, 2014

2013
Guided test generation for web applications.
Proceedings of the 35th International Conference on Software Engineering, 2013

Efficient and change-resilient test automation: an industrial case study.
Proceedings of the 35th International Conference on Software Engineering, 2013

The past present and future of design-technology co-optimization.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Efficiently scripting change-resilient tests.
Proceedings of the 20th ACM SIGSOFT Symposium on the Foundations of Software Engineering (FSE-20), 2012

Design benchmarking to 7nm with FinFET predictive technology models.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Automating test automation.
Proceedings of the 34th International Conference on Software Engineering, 2012

Exploring sub-20nm FinFET design with predictive technology models.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Workload-Aware Neuromorphic Design of the Power Controller.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Entering the circle of trust: developer initiation as committers in open-source projects.
Proceedings of the 8th International Working Conference on Mining Software Repositories, 2011

Outsourced, Offshored Software-Testing Practice: Vendor-Side Experiences.
Proceedings of the 6th IEEE International Conference on Global Software Engineering, 2011

Serving Information Needs in Business Process Consulting.
Proceedings of the Business Process Management - 9th International Conference, 2011

A workload-aware neuromorphic controller for dynamic power and thermal management.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010
Automated support for repairing input-model faults.
Proceedings of the ASE 2010, 2010

Workload-aware neuromorphic design of low-power supply voltage controller.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

BUGINNINGS: identifying the origins of a bug.
Proceedings of the Proceeding of the 3rd Annual India Software Engineering Conference, 2010

Automated Bug Neighborhood Analysis for Identifying Incomplete Bug Fixes.
Proceedings of the Third International Conference on Software Testing, 2010

Making defect-finding tools work for you.
Proceedings of the 32nd ACM/IEEE International Conference on Software Engineering, 2010

Debugging Model-Transformation Failures Using Dynamic Tainting.
Proceedings of the ECOOP 2010, 2010

From Informal Process Diagrams to Formal Process Models.
Proceedings of the Business Process Management - 8th International Conference, 2010

2009
The Predictive Technology Model in the Late Silicon Era and Beyond.
Found. Trends Electron. Des. Autom., 2009

Demystifying model transformations: an approach based on automated rule inference.
Proceedings of the 24th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2009

Fault localization and repair for Java runtime exceptions.
Proceedings of the Eighteenth International Symposium on Software Testing and Analysis, 2009

Efficient Testing of Service-Oriented Applications Using Semantic Service Stubs.
Proceedings of the IEEE International Conference on Web Services, 2009

Accurate Interprocedural Null-Dereference Analysis for Java.
Proceedings of the 31st International Conference on Software Engineering, 2009

Enabling resonant clock distribution with scaled on-chip magnetic inductors.
Proceedings of the 27th International Conference on Computer Design, 2009

2008
A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
Compact modeling of carbon nanotube transistor for early stage process-design exploration.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2006
Subsumption of program entities for efficient coverage and monitoring.
Proceedings of the Third International Workshop on Software Quality Assurance, 2006

2001
Interprocedural control dependence.
ACM Trans. Softw. Eng. Methodol., 2001

2000
Analysis and Testing of Programs with Exception Handling Constructs.
IEEE Trans. Software Eng., 2000

1999
Criteria for Testing Exception-Handling Constructs in Java Programs.
Proceedings of the 1999 International Conference on Software Maintenance, 1999

System-Dependence-Graph-Based Slicing of Programs with Arbitrary Interprocedural Control Flow.
Proceedings of the 1999 International Conference on Software Engineering, 1999

1998
Computation of Interprocedural Control Dependence.
Proceedings of ACM SIGSOFT International Symposium on Software Testing and Analysis, 1998

Analysis of Programs with Exception-Handling Constructs.
Proceedings of the 1998 International Conference on Software Maintenance, 1998


  Loading...