Kevin Stawiasz
Affiliations:- IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
According to our database1,
Kevin Stawiasz
authored at least 16 papers
between 1995 and 2015.
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Bibliography
2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
2014
5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8<sup>TM</sup> microprocessor.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Performance impact of through-silicon vias (TSVs) in three-dimensional technology measured by SRAM ring oscillators.
Proceedings of the ESSCIRC 2013, 2013
2011
A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS.
IEEE J. Solid State Circuits, 2011
2010
A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2008
IEEE J. Solid State Circuits, 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
2004
Experimental measurement of a novel power gating structure with intermediate power saving mode.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
2003
Minimizing inductive noise in system-on-a-chip with multiple power gating structures.
Proceedings of the ESSCIRC 2003, 2003
1998
IEEE J. Solid State Circuits, 1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
1995