Sarma B. K. Vrudhula
Orcid: 0000-0001-9278-2959
According to our database1,
Sarma B. K. Vrudhula
authored at least 183 papers
between 1993 and 2024.
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Bibliography
2024
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024
HeteroSwitch: Characterizing and Taming System-Induced Data Heterogeneity in Federated Learning.
CoRR, 2024
ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
2023
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems.
CoRR, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the 30th IEEE International Conference on High Performance Computing, 2023
2022
EdgeWise: Energy-efficient CNN Computation on Edge Devices under Stochastic Communication Delays.
ACM Trans. Embed. Comput. Syst., September, 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Computers, 2022
Tunable Precision Control for Approximate Image Filtering in an In-Memory Architecture with Embedded Neurons.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
Proceedings of the IEEE International Conference on Smart Computing, 2021
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
2020
ELSA: A Throughput-Optimized Design of an LSTM Accelerator for Energy-Constrained Devices.
ACM Trans. Embed. Comput. Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
2019
Optimizing User Satisfaction of Mobile Workloads Subject to Various Sources of Uncertainties.
IEEE Trans. Mob. Comput., 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
An Energy-Efficient FPGA Implementation of an LSTM Network Using Approximate Computing.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Proceedings of the 2019 IEEE International Conference on Big Data (IEEE BigData), 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler.
Integr., 2018
DORA: Optimizing Smartphone Energy Efficiency and Web Browser Performance under Interference.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs.
Proceedings of the International Conference on Computer-Aided Design, 2018
FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean Networks.
CoRR, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Demonstration of spike timing dependent plasticity in CBRAM devices with silicon neurons.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
2015
Thermal aware floorplanning incorporating temperature dependent wire delay estimation.
Microprocess. Microsystems, 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Fast and robust differential flipflops and their extension to multi-input threshold gates.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Dynamic and leakage power reduction of ASICs using configurable threshold logic gates.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Maximizing Quality of Coverage under Connectivity Constraints in Solar-Powered Active Wireless Sensor Networks.
ACM Trans. Sens. Networks, 2014
ACM Trans. Embed. Comput. Syst., 2014
Energy-Efficient Operation of Multicore Processors by DVFS, Task Migration, and Active Cooling.
IEEE Trans. Computers, 2014
Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture.
J. Parallel Distributed Comput., 2014
The Stochastic Loss of Spikes in Spiking Neural P Systems: Design and Implementation of Reliable Arithmetic Circuits.
Fundam. Informaticae, 2014
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
Proceedings of the 5th Annual International Conference on Biologically Inspired Cognitive Architectures, 2014
2013
REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs).
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
IEEE Trans. Computers, 2012
Proceedings of the IEEE INFOCOM 2012, Orlando, FL, USA, March 25-30, 2012, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the International Conference on Parallel Processing, 2011
A new balanced 4-moduli set {2<i><sup>k</sup></i>, 2<i><sup>n</sup></i> - 1, 2<i><sup>n</sup></i> + 1, 2<i><sup>n+1</sup></i>-1} and its reverse converter design for efficient fir filter implementation.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Reliability-aware thermal management for hard real-time applications on multi-core processors.
Proceedings of the Design, Automation and Test in Europe, 2011
2010
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Performance optimal speed control of multi-core processors under thermal constraints.
Proceedings of the Design, Automation and Test in Europe, 2009
Throughput optimal task allocation under thermal constraints for multi-core processors.
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
ACM Trans. Design Autom. Electr. Syst., 2008
A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory.
J. Low Power Electron., 2008
Scalable model for predicting the effect of negative bias temperature instability for reliable design.
IET Circuits Devices Syst., 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Analytical results for design space exploration of multi-core processors employing thread migration.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Current source based standard cell model for accurate signal integrity and timing analysis.
Proceedings of the Design, Automation and Test in Europe, 2008
Statistical waveform and current source based standard cell models for accurate timing analysis.
Proceedings of the 45th Design Automation Conference, 2008
Threshold Logic Gene Regulatory Model - Prediction of Dorsal-ventral Patterning and Hardware-based Simulation of Drosophila.
Proceedings of the First International Conference on Biomedical Electronics and Devices, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
ACM Trans. Embed. Comput. Syst., 2007
Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices.
J. Multiple Valued Log. Soft Comput., 2007
IEEE Des. Test Comput., 2007
Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Computation of Joint Timing Yield of Sequential Networks Considering Process Variations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 2007 International Conference on Compilers, 2007
2006
Joint Optimization of Transmit Power-Time and Bit Energy Efficiency in CDMA Wireless Sensor Networks.
IEEE Trans. Wirel. Commun., 2006
Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection.
J. Low Power Electron., 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Stochastic variational analysis of large power grids considering intra-die correlations.
Proceedings of the 43rd Design Automation Conference, 2006
High-level power management of embedded systems with application-specific energy cost functions.
Proceedings of the 43rd Design Automation Conference, 2006
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Proceedings of the 6th ACM Interational Symposium on Mobile Ad Hoc Networking and Computing, 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Leakage minimization of nano-scale circuits in the presence of systematic and random variations.
Proceedings of the 42nd Design Automation Conference, 2005
2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Stochastic analysis of interconnect performance in the presence of process variations.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 2004 International Conference on Compilers, 2004
2003
A model for battery lifetime analysis for organizing applications on a pocket computer.
IEEE Trans. Very Large Scale Integr. Syst., 2003
ACM Trans. Embed. Comput. Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
2002
ACM Trans. Design Autom. Electr. Syst., 2002
Algorithms for minimizing standby power in deep submicrometer, dual-V<sub>t</sub> CMOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
Battery-conscious task sequencing for portable devices including voltage/clock scaling.
Proceedings of the 39th Design Automation Conference, 2002
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002
2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001
An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
2000
1999
ACM Trans. Design Autom. Electr. Syst., 1999
Proceedings of the IEEE International Conference On Computer Design, 1999
1998
Integr. Comput. Aided Eng., 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Proceedings of the 1998 Design, 1998
1997
Proceedings of the Proceedings 8th IEEE International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype, 1997
Proceedings of the Proceedings 8th IEEE International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype, 1997
Proceedings of the 34st Conference on Design Automation, 1997
1996
IEEE Trans. Computers, 1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
1995
IEEE Trans. Computers, 1995
1994
EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
1993
IEEE Trans. Very Large Scale Integr. Syst., 1993
IEEE Trans. Very Large Scale Integr. Syst., 1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993