Haruo Kobayashi

According to our database1, Haruo Kobayashi authored at least 134 papers between 1992 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Pulse Coding Controlled Switching Converter that Generates Notch Frequency to Suit Noise Spectrum.
IEICE Trans. Commun., 2020

Activation Modeling and Classification of Voluntary and Imagery Movements From the Prefrontal fNIRS Signals.
IEEE Access, 2020


Analysis and Design of Multi-Tone Signal Generation Algorithms for Reducing Crest Factor.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

Accurate Testing of Precision Voltage Reference by DC-AC Conversion.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.
IEICE Electron. Express, 2019


Crest Factor Controlled Multi-Tone Signals for Analog/Mixed-Signal IC Testing.
Proceedings of the IEEE International Test Conference in Asia, 2019

Accurate and Fast Testing Technique of Operational Amplifier DC Offset Voltage in µV-Order by DC-AC Conversion.
Proceedings of the IEEE International Test Conference in Asia, 2019

Multi-Phase Full/Half Wave Type Resonant Converters with Automatic Current Balance against Element Variation.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

High-Resolution Low-Sampling-Rate Δ∑ ADC Linearity Short-Time Testing Algorithm.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Graphene Biosensor for Saliva Protein Adsorption.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Minimum Output Ripple and Fixed Operating Frequency Based on Modulation Injection for COT Ripple Control Converter.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Overshoot Cancelation Based on Balanced Charge-Discharge Time Condition for Buck Converter in Mobile Applications.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Flat Pass-Band Method with Two RC Band-Stop Filters for 4-Stage Passive RC Polyphase Filter in Low-IF Receiver Systems.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

EMI Noise Reduction and Output Ripple Cancellation for Full-Wave Type Soft-Switching Converter.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Pulse Coding Control Switching Converter with Adjustable Conversion Voltage Ratio Notch Frequency Generation in Noise Spectrum.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Optimization of High Reliability and Wide SOA 100 V LDMOS Transistor with Low Specific On-Resistance.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Fine Time Resolution TDC Architectures -Integral and Delta-Sigma Types.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Analog / Mixed-Signal / RF Circuits for Complex Signal Processing.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Automatic Correction of Current Imbalance for Multi-Phase COT Ripple-Based Control DC-DC Converter.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Systematic Construction of Resistor Ladder Network for N-ary DACs.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Analysis and Evaluation Method of RC Polyphase Filter.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Evaluation of Null Method for Operational Amplifier Short-Time Testing.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Frequency Estimation Sampling Circuit Using Analog Hilbert Filter and Residue Number System.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A Study on Loop Gain Measurement Method Using Output Impedance in DC-DC Buck Converter.
IEICE Trans. Commun., 2018

A Distortion Shaping Technique to Equalize Intermodulation Distortion Performance of Interpolating Arbitrary Waveform Generators in Automated Test Equipment.
J. Electron. Test., 2018

Innovative practices on test in Japan.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Low-Distortion One-Tone and Two-Tone Signal Generation Using AWG Over Full Nyquist Region.
Proceedings of the IEEE International Test Conference in Asia, 2018

Highly Efficient Waveform Acquisition Condition in Equivalent-Time Sampling System.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

Time-to-Digital Converter Architectures Using Two Oscillators with Different Frequencies.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
Using Distortion Shaping Technique to Equalize ADC THD Performance Between ATEs.
J. Electron. Test., 2017

A technique for dynamic range improvement of intermodulation distortion products for an Interpolating DAC-based Arbitrary Waveform Generator using a phase switching algorithm.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Low-distortion signal generation for analog/mixed-signal circuit testing with digital ATE.
Proceedings of the International Test Conference in Asia, 2017

DAC linearity improvement with layout technique using magic and latin squares.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

Two-phase soft-switching DC-DC converter with voltage-mode resonant switch.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

Constant on-time controlled four-phase buck converter via two ways of saw-tooth-wave circuit and PLL circuit.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

Equivalence between Nyquist and Routh-Hurwitz stability criteria for operational amplifier design.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

Estimation of circuit component values in buck converter using efficiency curve.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

Study of multistage digital oscilloscope trigger circuit.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

SAR TDC architecture for one-shot timing measurement with full digital implementation.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

Study of jitter generators for high-speed I/O interface jitter tolerance testing.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

Noise spread spectrum with adjustable notch frequency in complex pulse coding controlled DC-DC converters.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

Gray-code input DAC architecture for clean signal generation.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

Architecture of high performance successive approximation time digitizer.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

Delay-time suppression technique for DC/DC buck converter using voltage mode PWM control.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

Fibonacci sequence weighted SAR ADC as golden section search.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

SAR TDC Architecture with Self-Calibration Employing Trigger Circuit.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

Fundamental design tradeoff and performance limitation of electronic circuits based on uncertainty relationships.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
I-Q signal generation techniques for communication IC testing and ATE systems.
Proceedings of the 2016 IEEE International Test Conference, 2016

Rectangular Waveform Generation with Harmonics Suppression.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
A CMOS PWM Transceiver Using Self-Referenced Edge Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Transient Response Improvement of DC-DC Buck Converter by a Slope Adjustable Triangular Wave Generator.
IEICE Trans. Commun., 2015

Erratum to: A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator.
J. Electron. Test., 2015

SAR ADC design using Golden ratio weight algorithm.
Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015

A study on HCI induced gate leakage current model used for reliability simulations in 90nm n-MOSFETs.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Comparator circuits automation by combination of distributed genetic algorithm and HSPICE optimization.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

High efficiency single-inductor dual-output DC-DC converter with ZVS-PWM control.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Automatic design of doubly-terminated RC polyphase filters by using distributed genetic algorithm.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

High-frequency low-distortion signal generation algorithm with arbitrary waveform generator.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Flat passband gain design algorithm for 2nd-order RC polyphase filter.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Linearity enhancement algorithms for I-Q signal generation - DWA and self-calibration techniques.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

EMI reduction by analog noise spread spectrum in new ripple controlled converter.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Selectable notch frequencies of EMI spread spectrum using pulse modulation in switching converter.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Study on maximum electric field modeling used for HCI induced degradation characteristic of LDMOS transistors.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Finite aperture time effects in sampling circuit.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Fibonacci sequence weighted SAR ADC algorithm and its DAC topology.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A low-offset cascaded time amplifier with reconfigurable inter-stage connection.
IEICE Electron. Express, 2014

Analog/mixed-signal circuit design in nano CMOS era.
IEICE Electron. Express, 2014

A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator.
J. Electron. Test., 2014

Low-distortion signal generation for ADC testing.
Proceedings of the 2014 International Test Conference, 2014

2013
A Feed-Forward Time Amplifier Using a Phase Detector and Variable Delay Lines.
IEICE Trans. Electron., 2013

Two-Tone Signal Generation for ADC Testing.
IEICE Trans. Electron., 2013

Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption.
IEICE Electron. Express, 2013

Multi-bit Sigma-Delta TDC Architecture with Improved Linearity.
J. Electron. Test., 2013

Digital Compensation for Timing Mismatches in Interleaved ADCs.
Proceedings of the 22nd Asian Test Symposium, 2013

An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators.
Proceedings of the 22nd Asian Test Symposium, 2013

Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation.
IEEE J. Solid State Circuits, 2012

Low-Distortion Sinewave Generation Method Using Arbitrary Waveform Generator.
J. Electron. Test., 2012

A clock jitter reduction circuit using gated phase blending between self-delayed clock edges.
Proceedings of the Symposium on VLSI Circuits, 2012

A New Procedure for Measuring High-Accuracy Probability Density Functions.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Post-Silicon Jitter Measurements.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Two-Tone Signal Generation for Communication Application ADC Testing.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Multi-bit sigma-delta TDC architecture with self-calibration.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

Single inductor dual output DC-DC converter design with exclusive control.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

Digitally-controlled Gm-C bandpass filter.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

DC-DC converter with continuous-time feed-forward Sigma-Delta modulator control.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme.
IEICE Trans. Electron., 2011

Design for Testability That Reduces Linearity Testing Time of SAR ADCs.
IEICE Trans. Electron., 2011

Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements.
Proceedings of the International SoC Design Conference, 2011

An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Noise-Coupled Image Rejection Architecture of Complex Bandpass DeltaSigmaAD Modulator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

SAR ADC Algorithm with Redundancy and Digital Error Correction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Timing skew compensation technique using digital filter with novel linear phase condition.
Proceedings of the 2011 IEEE International Test Conference, 2010

Background calibration algorithm for pipelined ADC with open-loop residue amplifier using split ADC structure.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

ADC linearity test signal generation algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Single inductor DC-DC converter with bipolar outputs using charge pump.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Non-binary SAR ADC with digital error correction for low power applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

SAR ADC that is configurable to optimize yield.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Stochastic TDC architecture with self-calibration.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Analysis of Coupled Inductors for Low-Ripple Fast-Response Buck Converter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Cross-Noise-Coupled Architecture of Complex Bandpass DeltaSigmaAD Modulator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

EMI Reduction by Spread-Spectrum Clocking in Digitally-Controlled DC-DC Converters.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Foreword.
IEICE Trans. Electron., 2009

Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A Time-to-Digital Converter with small circuitry.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Novel Architecture of Feedforward Second-Order Multibit Delta-Sigma-AD Modulator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Analysis of coupled inductors for low-ripple fast-response buck converter.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

SAR ADC algorithm with redundancy.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

High-resolution DPWM generator for digitally controlled DC-DC converters.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

ΔΣAD modulator for low power application.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

New architecture for envelope-tracking power amplifier for base station.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Total Harmonic Distortion Measurement System of Electronic Devices up to 100 MHz With Remarkable Sensitivity.
IEEE Trans. Instrum. Meas., 2007

A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm.
IEICE Trans. Electron., 2007

A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A Practical Analog BIST Cooperated with an LSI Tester.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

2005
Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths.
IEICE Trans. Electron., 2005

A practical BIST circuit for analog portion in deep sub-micron CMOS system LSI.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass \Delta\SigmaAD Modulators.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2001
ADC standard and testing in Japanese industry.
Comput. Stand. Interfaces, 2001

Channel linearity mismatch effects in time-interleaved ADC systems.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1998
Vision chip architecture with light adaptation mechanism.
Artif. Life Robotics, 1998

Spatial and temporal stability of vision chips including parasitic inductances and capacitances.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1995
Two-dimensional spatio-temporal dynamics of analog image processing neural networks.
IEEE Trans. Neural Networks, 1995

Light-adaptive architectures for regularization vision chips.
Neural Networks, 1995

Error Correction Algorithm for Folding/Interpolation ADC.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1993
Image processing regularization filters on layered architecture.
Neural Networks, 1993

1992
Spatial versus temporal stability issues in image processing neuro chips.
IEEE Trans. Neural Networks, 1992


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