Sébastien Pillement
Orcid: 0000-0002-9160-2896Affiliations:
- University of Nantes, France
According to our database1,
Sébastien Pillement
authored at least 88 papers
between 1996 and 2025.
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Bibliography
2025
ACM Trans. Reconfigurable Technol. Syst., September, 2025
A Study in Specification and Hardware Runtime Verification of Critical Embedded Software.
IEEE Trans. Dependable Secur. Comput., 2025
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025
Proceedings of the Rapid Simulation and Performance Evaluation for Design Workshop, 2025
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2025
2024
Runtime Task Scheduling for FPGA-Based Embedded Systems Using Just-in-Time Bitstream Prefetching.
IEEE Access, 2024
2023
Proceedings of the 19th International Conference on Synthesis, 2023
Fast Yet Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms.
Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
Proceedings of the Design and Architecture for Signal and Image Processing, 2022
2021
0-1 ILP-based run-time hierarchical energy optimization for heterogeneous cluster-based multi/many-core systems.
J. Syst. Archit., 2021
Experimental Evaluation of Statistical Model Checking Methods for Probabilistic Timing Analysis of Multiprocessor Systems.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoC.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
System-Level Modeling and Simulation of MPSoC Run-Time Management Using Execution Traces Analysis.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Experimental Evaluation of Probabilistic Execution-Time Modeling and Analysis Methods for SDF Applications on MPSoCs.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Mapping and Frequency Joint Optimization for Energy Efficient Execution of Multiple Applications on Multicore Systems.
Proceedings of the 2019 Conference on Design and Architectures for Signal and Image Processing, 2019
2018
High-Level Reliability Evaluation of Reconfiguration-Based Fault Tolerance Techniques.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
Proceedings of the 14th European Dependable Computing Conference, 2018
2017
Cooperative Spectrum Sensing with Small Sample Size in Cognitive Wireless Sensor Networks.
Wirel. Pers. Commun., 2017
Sensors, 2017
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017
2016
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016
2015
A Robust and Energy Efficient Cooperative Spectrum Sensing Scheme in Cognitive Wireless Sensor Networks.
Netw. Protoc. Algorithms, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the IEEE International Conference on Communication, 2015
2014
Design of the coarse-grained reconfigurable architecture DART with on-line error detection.
Microprocess. Microsystems, 2014
Microprocess. Microsystems, 2014
Proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2014
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
2013
Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor.
IEEE Trans. Computers, 2013
Des. Autom. Embed. Syst., 2013
Proceedings of the 8th International Design and Test Symposium, 2013
2012
Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Gradient - An adaptive fault-tolerant routing algorithm for 2D mesh Network-on-Chips.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
2011
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network.
J. Syst. Archit., 2011
Communication service for hardware tasks executed on dynamic and partial reconfigurable resources.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Parallel Evaluation of Hopfield Neural Networks.
Proceedings of the NCTA 2011, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
2010
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Microelectron. J., 2010
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures.
Int. J. Reconfigurable Comput., 2010
IEEE Commun. Lett., 2010
Mesh and Fat-Tree comparison for dynamically reconfigurable applications.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Conception d'architectures reconfigurables dynamiquement : Du silicium au système. (Dynamically reconfigurable architectures: From silicon to system management).
, 2010
2009
Int. J. Reconfigurable Comput., 2009
A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
High-Level Exploration for Dynamic Reconfiguration Management.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
2008
EURASIP J. Embed. Syst., 2008
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
2007
Tech. Sci. Informatiques, 2007
Proceedings of the International Joint Conference on Neural Networks, 2007
Proceedings of the 15th European Signal Processing Conference, 2007
Proceedings of the Architecture of Computing Systems, 2007
2006
Clear Stream towards Dynamically Reconfigurable Systems on Chip.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Tech. Sci. Informatiques, 2005
Exploring RTOS issues with a high-level model of a reconfigurable SoC platform.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
A low-power and high-speed quaternary interconnection link using efficient converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
Mapping future generation mobile telecommunication applications on a dynamically reconfigurable arcidtecture.
Proceedings of the IEEE International Conference on Acoustics, 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
2001
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals.
Proceedings of the SOC Design Methodologies, 2001
1999
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999
Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies.
Proceedings of the VLSI: Systems on a Chip, 1999
1996
Proceedings of the Field-Programmable Logic, 1996