Gauthaman Murali
Orcid: 0000-0003-0146-4977
According to our database1,
Gauthaman Murali
authored at least 22 papers
between 2019 and 2025.
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Bibliography
2025
3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3-D DNN Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., February, 2025
System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025
A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
Design Methodology And Electronic Design Automation Techniques For Heterogeneous 3D Machine Learning Accelerators.
PhD thesis, 2024
Hetero-3D: Maximizing Performance and Power Delivery Benefits of Heterogeneous 3D ICs.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
2023
On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023
A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers.
ACM Trans. Design Autom. Electr. Syst., September, 2023
3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3D DNN Accelerators.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Heterogeneous 3D ICs: Current Status and Future Directions for Physical Design Technologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Proceedings of the VLSI-SoC: Design Trends, 2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2019
Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019